X9440
Characteristics subject to change without notice.
6 of 22
REV 1.0 2/27/01
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Four of the ten instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 4. These two-byte instructions
exchange data between the wiper counter register or
analog control register and one of the data registers. A
transfer from a data register to a wiper counter register
or analog control register is essentially a write to a
static RAM. The response of the wiper to this action will
be delayed t
WRL
. A transfer from the wiper counter reg-
ister current wiper position to a data register is a write
to non volatile memory and takes a minimum of t
WR
to
complete. The transfer can occur between one of the
two potentiometers or one of the two voltage compara-
tors and one of its associated registers; or it may occur
globally, wherein the transfer occurs between both of
the potentiometers and voltage comparators and one
of their associated registers.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9440; either between the host and one
of the data registers or directly between the host and
the wiper counter and analog control registers. These
instructions are: Read Wiper Counter Register or Ana-
log Control Register, read the current wiper position of
the selected pot or the comparator control bits, Write
Wiper Counter Register or Analog Control Register, i.e.
change current wiper position of the selected pot or
control the voltage comparator; Read Data Register,
read the contents of the selected non volatile register;
Write Data Register, write a new value to the selected
data register. The bit structures of the instructions are
shown in Figure 9.
The sequences of the three byte operations are shown
in Figure 5 and Figure 6.
The bit structures of the instructions and the descrip-
tion of the instructions are shown in Figure 10.
Figure 4. Two-Byte Command Sequence
Figure 5. Three-Byte Command Sequence (Write)
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1
R0
P1 P0
SCK
SI
CS
0
1
0
1
A1 A0
I3
I2
I1
I0
R1 R0 P1 P0
SCL
SI
0
0
D5 D4 D3 D2
D1 D0
CS
0
0