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參數(shù)資料
| 型號： | X84256S825 |
| 英文描述： | Serial EEPROM |
| 中文描述： | 串行EEPROM |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 145K |
| 代理商： | X84256S825 |
X84256
Characteristics subject to change without notice.
3 of 13
REV 1.1 11/22/00
www.xicor.com
Read Sequence
A read sequence consists of sending a 16-bit address,
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and
CE LOW, OE HIGH) to the part without a read cycle
between the write cycles. The address is sent serially,
most significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restric-
tions, and the processor is free to perform other tasks
on the bus whenever the device CE pin is HIGH. Once
the 16 address bits are sent, a byte of data can be read
on the I/O line by issuing 8 separate read cycles (OE
and CE LOW, WE HIGH). At this point, writing a ‘1’ will
terminate the read sequence and enter the low power
standby state, otherwise the device will await further
reads in the sequential read mode.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read.
The data stored in the memory at the next address can
be read sequentially by continuing to issue read
cycles. When the highest address in the array is
reached, the address counter rolls over to address
$0000 and reading may be continued indefinitely.
Reset Sequence
The reset sequence resets the device and sets an
internal write enable latch. A reset sequence can be
sent at any time by performing a read/write “0”/read
operation (see Figs. 1 and 2). This breaks the multiple
read or write cycle sequences that are normally used
to read from or write to the part. The reset sequence
can be used at any time to interrupt or end a sequential
read or page load. As soon as the write “0” cycle is
complete, the part is reset (unless a nonvolatile write
cycle is in progress). The second read cycle in this
sequence, and any further read cycles, will read a
HIGH on the l/O pin until a valid read sequence (which
includes the address) is issued. The reset sequence
must be issued at the beginning of both read and write
sequences to be sure the device initiates these opera-
tions properly.
Write Sequence
A nonvolatile write sequence consists of sending a
reset sequence, a 16-bit address, up to 64-bytes of
data, and then a special “start nonvolatile write cycle”
command sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write
enable latch. The address is written serially by issuing
16 separate write cycles (WE and CE LOW, OE HIGH)
to the part without any read cycles between the writes.
The address is sent serially, most significant bit first, on
the l/O pin. Up to 64-bytes of data are written by issu-
ing a multiple of 8 write cycles. Again, no read cycles
are allowed between writes.
The nonvolatile write cycle is initiated by issuing a spe-
cial read/write “1”/read sequence. The first read cycle
ends the page load, then the write “1” followed by a
read starts the nonvolatile write cycle. The device rec-
ognizes 64-byte pages (e.g., beginning at addresses
XXXXXXXXX 000000 for X84256).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
page, where data loading can continue. For this rea-
son, sending more than 512 consecutive data bits will
result in overwriting previous data.
A nonvolatile write cycle will not start if a partial or
incomplete write sequence is issued. The internal write
enable latch is reset when the nonvolatile write cycle is
completed and after an invalid write to prevent inad-
vertent writes. Note that this sequence is fully static,
with no special timing restrictions. The processor is
free to perform other tasks on the bus whenever the
chip enable pin (CE) is HIGH.
相關(guān)PDF資料 |
PDF描述 |
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| X84256V1425 | Serial EEPROM |
| X86-64 | x86-64 - Advanced Micro Devices. Inc. x86-64TM Technology White Paper |
| X88064 | E2 Micro-Peripheral |
| X88064P | E2 Micro-Peripheral |
| X88064P-60 | E2 Micro-Peripheral |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X84256S8I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:UPort Saver EEPROM |
| X84256S8I-1.8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:UPort Saver EEPROM |
| X84256S8I-2.5 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:UPort Saver EEPROM |
| X84256V14 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:UPort Saver EEPROM |
| X84256V14-1.8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:UPort Saver EEPROM |
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