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參數(shù)資料
| 型號： | X4645V8I-4.5A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | CPU Supervidor with 64K EEPROM |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 408K |
| 代理商： | X4645V8I-4.5A |
X4643/5 – Preliminary Information
Characteristics subject to change without notice.
15 of 22
REV 1.26 4/30/02
www.xicor.com
CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V)
Notes:
(4) This parameter is periodically sampled and not 100% tested.
Symbol
C
OUT
(4)
C
IN
(4)
Parameter
Max.
8
6
Unit
pF
pF
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Output Capacitance (SDA, RST/RST)
Input Capacitance (SCL, WP)
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
SDA
or
RESET
1533
100pF
5V
For V
OL
= 0.4V
and I
OL
= 3 mA
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
0.1V
CC
to 0.9V
CC
10ns
0.5V
CC
Standard output load
A.C. CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified)
Notes:
(1) Typical values are for T
A
= 25°C and V
CC
= 5.0V
(2) Cb = total capacitance of one bus line in pF.
Symbol
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
t
SU:WP
t
HD:WP
Cb
Parameter
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
Max.
400
Unit
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
μs
μs
pF
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
0.9
20 + .1Cb
20 + .1Cb
0.6
0
300
300
400
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