參數(shù)資料
型號: X40030S14IZ-B
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Triple Voltage Monitor with Integrated CPU Supervisor
中文描述: 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-14
文件頁數(shù): 19/24頁
文件大?。?/td> 360K
代理商: X40030S14IZ-B
19
FN8114.1
May 25, 2006
TIMING DIAGRAMS
Bus Timing
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Note:
(1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Symbol
t
WC(1)
Parameter
Write Cycle Time
Min.
Typ.
5
Max.
10
Unit
ms
t
SU:STO
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
R
t
DH
t
AA
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1
Clk 9
Slave Address Byte
START
SCL
SDA
t
WC
8
th
Bit of Last Byte
ACK
Stop
Condition
Start
Condition
X40030, X40031, X40034, X40035
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