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參數(shù)資料
| 型號(hào)： | X40030S14IZ-B |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Triple Voltage Monitor with Integrated CPU Supervisor |
| 中文描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-14 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 360K |
| 代理商： | X40030S14IZ-B |
11
FN8114.1
May 25, 2006
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
– Write one byte value to the Control Register that has
all the control bits set to the desired state. The Con-
trol register can be represented as
qxys
001
r
in
binary, where
xy
are the WD bits,
s
is the BP bit and
qr
are the power up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a
nonvolatile write cycle it will take up to 10ms (max.)
to complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(
qxys 0
11
r
) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, or
power cycling the device or attempting a write to a
write protected block.
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
Notes: 1. t
PURST
is set to 200ms as factory default.
2. Watch Dog Timer bits are shipped
disabled.
FAULT DETECTION REGISTER (FDR)
The Fault Detection Register provides the user the
status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the
control register to access this FDR.
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
1.4 seconds
200 milliseconds
25 milliseconds
disabled (factory setting)
7
6
5
4
3
2
0
1
0
0
0
LV1F
LV2F
LV3F
WDF
MRF
X40030, X40031, X40034, X40035
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