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參數(shù)資料
| 型號： | X3211 |
| 廠商： | 友順科技股份有限公司 |
| 英文描述： | LINEAR INTEGRATED CIRCUIT |
| 中文描述： | 線性集成電路 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 198K |
| 代理商： | X3211 |
UTC X3211
LINEAR INTEGRATED CIRCUIT
UTC
UNISONIC TECHNOLOGIES CO., LTD.
7
QW-R122-004,C
FUNCTIONAL DIAGRAM
Negative
Supply
Gen.
+
-
+
-
+
-
C
NB1
C
NB2
C
NB
C
SUB
C
SUB
G
ND
G
N
D
N
O
N
I
D
Sense
+
-
Set
S
ID
V
D
Set
Vcc
R
CAL
R
CAL
20
μ
A
I
D
Set
FUNCTIONAL DESCRIPTION
The X3211 provides all the bias requirements for external FETs, including the generation of the negative supply
required for gate biasing, from the single supply voltage. It contains 3 such stages. The negative rail generator is
common to all devices.
The drain voltage of the external FET Q
N
is set by the X3211 device to its normal operating voltage. This is
determined by the on board V
D
Set reference, the X3211 provides nominally 2 volts .
The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier driving the gate of
the FET adjusts the gate voltage of Q
N
so that the drain current taken matches the current called for by an external
resistor R
CAL
.
Since the FET is a depletion mode transistor, it is usually necessary to drive its gate negative with respect to ground
to obtain the required drain current. To provide this capability powered from a single positive supply, the device
includes a low current negative supply generator. This generator uses an internal oscillator and two external
capacitors, C
NB
and C
SUB
.
The following schematic shows the function of the Vpol input. Only one of the two external FETs numberd Q1 and
Q2 are powered at any one time, their selection is controlled by the input Vpol. This input is designed to be wired to
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