參數(shù)資料
型號: X28HT010W
廠商: INTERSIL CORP
元件分類: DRAM
英文描述: 5V, Byte Alterable EEPROM
中文描述: 128K X 8 EEPROM 5V, 200 ns, UUC
封裝: WAFER
文件頁數(shù): 11/20頁
文件大?。?/td> 444K
代理商: X28HT010W
11
FN8105.1
February 12, 2007
Equivalent A.C. Load Circuit
Symbol Table
Endurance and Data Retention
PARAMETER
MIN
MAX
UNIT
Endurance
10,000
Cycles per byte
Endurance
100,000
Cycles per page
Data Retention
100
Years
A.C. Conditions of Test
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input and output timing levels
1.5V
Mode Selection
CE
OE
WE
MODE
I/O
POWER
L
L
H
Read
D
OUT
Active
L
H
L
Write
D
IN
Active
H
X
X
Standby and
Write Inhibit
High Z
Standby
X
L
X
Write Inhibit
X
X
H
Write Inhibit
5V
1.92k
Ω
100pF
Output
1.37k
Ω
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
AC Electrical Specifications
Over the recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
X28C010-12
X28C010-15
X28C010-20,
X28HT010W
X28C010-25
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
READ CYCLE LIMITS
t
RC
Read cycle time
120
150
200
250
ns
t
CE
Chip enable access time
120
150
200
250
ns
t
AA
Address access time
120
150
200
250
ns
t
OE
Output enable access time
50
50
50
50
ns
t
LZ
(Note 4)
CE LOW to active output
0
0
0
0
ns
t
OLZ
(Note 4)
OE LOW to active output
0
0
0
0
ns
t
HZ
(Note 4)
CE HIGH to high Z output
50
50
50
50
ns
t
OHZ
(Note 4)
OE HIGH to high Z output
50
50
50
50
ns
t
OH
Output hold from address change
0
0
0
0
ns
X28C010, X28HT010
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