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參數(shù)資料
| 型號(hào)： | X28HC64J-50 |
| 英文描述： | 5 Volt, Byte Alterable E2PROM |
| 中文描述： | 5伏，可變E2PROM的字節(jié) |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 112K |
| 代理商： | X28HC64J-50 |
X28HC64
9
SYSTEM CONSIDERATIONS
Because the X28HC64 is frequently used in large memory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit it is recommended that
CE
be
decoded from the address bus and be used as the
primary device selection input. Both
OE
and
WE
would
then be common among all devices in the array. For a
read operation, this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28HC64 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling
CE
will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1
μ
F high fre-
quency ceramic capacitor be used between V
CC
and
V
SS
at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7
μ
F electrolytic
bulk capacitor be placed between V
CC
and V
SS
for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Normalized I
CC
(RD) by Temperature
Over Frequency
Normalized I
CC
(RD) @ 25% Over
the V
CC
Range and Frequency
1.4
1.2
0.8
0.4
0.6
0.2
1.0
0
10
20
- 55
°
C
+ 25
°
C
+ 125
°
C
IC
N
FREQUENCY (MHz)
3857 FHD F20.1
5.5 VCC
1.4
1.2
0.8
0.4
0.6
0.2
1.0
0
10
20
IC
N
FREQUENCY (MHz)
3857 FHD F21.1
4.5 VCC
5.0 VCC
5.5 VCC
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PDF描述 |
|---|---|
| X28HC64JI-12 | 5 Volt, Byte Alterable E2PROM |
| X28HC64JI-50 | 5 Volt, Byte Alterable E2PROM |
| X28HC64JI-70 | 5 Volt, Byte Alterable E2PROM |
| X28HC64JI-90 | 5 Volt, Byte Alterable E2PROM |
| X28HC64JM-12 | 5 Volt, Byte Alterable E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X28HC64J-55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
| X28HC64J-70 | 制造商:Intersil Corporation 功能描述:EEPROM PARALLEL 64KBIT 8KX8 5V 32PLCC - Rail/Tube |
| X28HC64J-70T1 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 8K X 8, CMOS 電可擦除可編程只讀存儲(chǔ)器, SDP, 32 PLCC, COM.,70NS T & R RoHS:否 制造商:Intersil 存儲(chǔ)容量: 組織: 數(shù)據(jù)保留: 最大時(shí)鐘頻率: 最大工作電流: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| X28HC64J-90 | 功能描述:IC EEPROM 64KBIT 90NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
| X28HC64J-90T1 | 制造商:Intersil Corporation 功能描述:EEPROM PARALLEL 64KBIT 8KX8 5V 32PLCC - Tape and Reel |
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