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參數(shù)資料
| 型號(hào)： | X24325VM-2.7 |
| 英文描述： | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| 中文描述： | 先進(jìn)的2線串行e的2座門鎖TM保護(hù)胎膜早破 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大小： | 79K |
| 代理商： | X24325VM-2.7 |
X24325
8
Figure 10. Typical System Configuration
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24325 continues to
output data for each acknowledge received. The read
operation is terminated by the master; by not
responding with an acknowledge and then issuing a
stop condition.
The data output is sequential, with the data from
address n followed by the data from n + 1. The address
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
during one operation. At the end of the address space
(address 4095), the counter “rolls over” to 0 and the
X24325 continues to output data for each acknowledge
received. Refer to Figure 9 for the address,
acknowledge and data transfer sequence.
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24325
SLAVE
ADDRESS
A
C
K
6552 ILL F13
A
C
K
DATA n+x
S
T
O
P
P
DATA n
A
C
K
DATA n+1
A
C
K
DATA n+2
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
PULL-UP
RESISTORS
SDA
SCL
VCC
6552 ILL F14
Figure 9. Sequential Read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24325P-2.7 | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325 | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325P | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325PI | IC ADJ SHUNT REG LV SOT-23-3 |
| X24325PM | IC ADJ SHUNT REG LV SOT-23-3 |
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