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參數資料
| 型號： | X24325VM-2.7 |
| 英文描述： | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| 中文描述： | 先進的2線串行e的2座門鎖TM保護胎膜早破 |
| 文件頁數： | 12/17頁 |
| 文件大小： | 79K |
| 代理商： | X24325VM-2.7 |
X24325
12
A.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits
6552 FRM T09.1
POWER-UP TIMING
(4)
6552 FRM T10
Notes:
(4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
Symbol
f
SCL
T
I
Parameter
Min.
0
Max.
100
Units
KHz
SCL Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL LOW to SDA Data Out Valid
100
ns
t
AA
t
BUF
0.3
3.5
μ
s
Time the Bus Must Be Free Before a
New Transmission Can Start
Start Condition Hold Time
4.7
μ
s
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
4
μ
s
Clock LOW Period
4.7
μ
s
Clock HIGH Period
4
μ
s
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
4.7
μ
s
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
0
μ
s
Data In Setup Time
250
ns
SDA and SCL Rise Time
1
μ
s
SDA and SCL Fall Time
300
ns
Stop Condition Setup Time
4.7
μ
s
Data Out Hold Time
300
ns
Symbol
t
PUR
t
PUW
Parameter
Max.
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
5
ms
A.C. CONDITIONS OF TEST
6552 FRM T08.1
Input Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input Rise and
Fall Times
Input and Output
Timing Levels
10ns
V
CC
X 0.5
EQUIVALENT A.C. LOAD CIRCUIT
6552 ILL F16
5V
1533
100pF
OUTPUT
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