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參數(shù)資料
| 型號(hào)： | X24325VM-2.7 |
| 英文描述： | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| 中文描述： | 先進(jìn)的2線串行e的2座門鎖TM保護(hù)胎膜早破 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | X24325VM-2.7 |
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X24325
13
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the
Bus Timing
X24325 bus interface circuits are disabled, SDA is
allowed to remain HIGH, and the device does not
respond to its slave address.
Bus Timing
6552 ILL F17
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tLOW
tSU:STO
tR
tBUF
SCL
SDA IN
SDA OUT
tDH
tAA
tF
tHIGH
Write Cycle Limits
6552 FRM T11.1
Symbol
t
WR(6)
Parameter
Min.
Typ.
(5)
Max.
Units
Write Cycle Time
5
10
ms
6552 ILL F18
SCL
SDA
8th BIT
WORD n
ACK
tWR
STOP
CONDITION
START
CONDITION
Notes: (5) Typical values are for T
A
= 25
°
C and nominal supply voltage (5V).
(6) t
WR
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
6552 ILL F19
120
100
80
40
60
20
20
40
60
80 100 120
0
0
R
)
BUS CAPACITANCE (pF)
MIN.
RESISTANCE
MAX.
RESISTANCE
RMAX =CBUS
tR
RMIN =
IOL MIN
VCC MAX=1.8K
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24325P-2.7 | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325 | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325P | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325PI | IC ADJ SHUNT REG LV SOT-23-3 |
| X24325PM | IC ADJ SHUNT REG LV SOT-23-3 |
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