參數(shù)資料
型號: X24256ZI-1.8
英文描述: 30V Single N-Channel HEXFET Power MOSFET in a D2-Pak package; A IRL7833S with Standard Packaging
中文描述: EEPROM的
文件頁數(shù): 12/18頁
文件大?。?/td> 144K
代理商: X24256ZI-1.8
X24256
Characteristics subject to change without notice.
12 of 18
S0, S1, and WP Pin Timing
Write Cycle Limits
Notes:
(6) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24256 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
Write CycleTiming
Symbol
Parameter
Min.
Typ.
Max.
Units
T
WC
(6)
Write Cycle Time
5
10
ms
t
SU: S0, S1, WP
SCL
SDA IN
S0, S1, and WP
Slave Address Byte
Clk 1
Clk 9
t
HD: S0, S1, WP
SCL
SDA
8th BIT
WORD n
ACK
tWC
STOP
CONDITION
START
CONDITION
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