FN8102.3 April 14, 2006 ation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 14 for the address, acknow" />
參數(shù)資料
型號(hào)： X1288S16
廠(chǎng)商： Intersil
文件頁(yè)數(shù)： 13/27頁(yè)
文件大小： 0K
描述： IC RTC/CAL/CPU SUP EE 16-SOIC
標(biāo)準(zhǔn)包裝： 47
類(lèi)型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器
時(shí)間格式： HH:MM:SS:hh（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線(xiàn)串口
電源電壓： 4.5 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
20
FN8102.3
April 14, 2006
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 14 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1288 resets itself without per-
forming the write. The contents of the array are not
affected.
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1288 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1288 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1288 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 16.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1288 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power-on reset
can download the entire contents of memory starting
at the first location.Upon receipt of the Slave Address
Byte with the R/W bit set to one, the X1288 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issu-
ing a stop condition. Refer to Figure 15 for the
address, acknowledge, and data transfer sequence.
Word
Address 0
S
t
a
r
t
S
t
o
p
Slave
Address
Word
Address 1
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
1
≤ n ≤ 128 for EEPROM array
1
≤ n ≤ 8 for CCR
1
10
FIGURE 14. PAGE WRITE SEQUENCE
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
FIGURE 15. CURRENT ADDRESS READ SEQUENCE
X1288
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