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參數(shù)資料
| 型號： | X1288S16 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CAL/CPU SUP EE 16-SOIC |
| 標準包裝： | 47 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，監(jiān)控器，監(jiān)視計時器 |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 管件 |
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19
FN8102.3
April 14, 2006
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 11.
After loading the entire Slave Address Byte from the
SDA bus, the X1288 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power-
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master must supply the 2 Word Address
Bytes as shown in Figure 11.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is if the random read is from
the array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the
Clock/Control Registers, the slave byte must be
1101111x in both places.
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1288 responds with
an acknowledge. After receiving both address bytes
the X1288 awaits the eight bits of data. After receiving
the 8 data bits, the X1288 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1288 then
begins an internal write cycle of the data to the nonvol-
atile memory. During the internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 12.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1288 will not initiate an internal
write cycle, and will continue to ACK commands.
Page Write
The X1288 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 127
more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (Note: Prior to writ-
ing to the CCR, the master must write a 02h, then 06h
to the status register in two preceding operations to
enable the write operation. See “Writing to the
Clock/Control Registers.”
After the receipt of each byte, the X1288 responds with
an acknowledge, and the address is internally incre-
mented by one. When the counter reaches the end of
the page, it “rolls over” and goes back to the first
address on the same page. This means that the master
can write 128 bytes to a memory array page or 8 bytes
to a CCR section starting at any location on that page.
For example, if the master begins writing at location 105
of the memory and loads 30 bytes, then the first 23
bytes are written to addresses 105 through 127, and the
last 7 bytes are written to columns 0 through 6. After-
wards, the address counter would point to location 7 on
the page that was just written. If the master supplies
more than the maximum bytes in a page, then the previ-
ously loaded data is over written by the new data, one
byte at a time. Refer to Figure 13.
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the X1288 to begin
the nonvolatile write cycle. As with the byte write oper-
X1288
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