- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372528 > X1242S8 200V Single N-Channel HEXFET Power MOSFET in a SO-8 package; A IRF7450 with Standard Packaging PDF資料下載
參數(shù)資料
| 型號(hào)： | X1242S8 |
| 英文描述： | 200V Single N-Channel HEXFET Power MOSFET in a SO-8 package; A IRF7450 with Standard Packaging |
| 中文描述： | 集成電路表面貼裝與EEPROM的時(shí)鐘 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 119K |
| 代理商： | X1242S8 |
X1242 – Preliminary Information
Characteristics subject to change without notice.
3 of 24
REV 1.1.3 10/15/00
www.xicor.com
time is latched by the read command (falling edge of
the clock on the ACK bit prior to RTC data output) into
a separate latch to avoid time changes during the read
operation. The clock continues to run. Alarms occur-
ring during a read are unaffected by the read opera-
tion.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the first “one second” clock cycle after
the stop bit. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only acces-
sible following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
CCR Access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes)
2. Alarm 1 (8 bytes)
3. Control (1 byte)
4. Real Time Clock (8 bytes)
5. Status (1 byte)
Sections 1) through 3) are nonvolatile and Sections 4)
and 5) are volatile. Each register is read and written
through buffers. The nonvolatile portion (or the counter
portion of the RTC) is updated only if RWEL is set and
only after a valid write operation and stop bit. A
sequential read or page write operation provides
access to the contents of only one section of the CCR
per operation. Access to another section requires a
new operation. Continued reads or writes, once reach-
ing the end of a section, will wrap around to the start of
the section. A read or page write can begin at any
address in the CCR.
Section 5) is a volatile register. It is not necessary to
set the RWEL bit prior to writing the status register.
Section 5) supports a single byte read or write only.
Continued reads or writes from this section terminates
the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24-hour time selection bit. The enable
bits specify which registers to use in the comparison
between the Alarm and Real Time Registers. For
example:
– The user can set the X1242 to alarm every Wednes-
day at 8:00AM by setting the EDWn, the EHRn and
EMNn enable bits to ‘1’ and setting the DWAn, HRAn
and MNAn Alarm registers to 8:00AM Wednesday.
– A daily alarm for 9:30PM results when the EHRn
and EMNn enable bits are set to ‘1’ and the HRAn
and MNAn registers set 9:30PM.
– Setting the EMOn bit in combination with other
enable bits and a specific alarm time, the user can
establish an alarm that triggers at the same time
once a year.
When there is a match, an alarm flag is set. The occur-
rence of an alarm can only be determined by polling
the AL0 and AL1 bits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X1242 | Real Time Clock/Calendar/Alarms/CPU Supervisor(實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/帶EEPROM的監(jiān)控) |
| x1243(中文) | Real Time Clock/Calendar/Alarm with EEPROM(帶EEPROM的實(shí)時(shí)時(shí)鐘/日歷/鬧鐘) |
| X12xx-EVM(中文) | Xicor RTC X12xx-EVM User Guide(XICOR RTC X12xx-EVM評(píng)估板使用說明) |
| X187 | TEMPERATURSICHERUNG 187GRAD 5ST |
| X25 | 40V Single N-Channel HEXFET Power MOSFET in a D2-Pak package; A IRL1004S with Standard Packaging |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X1243 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock/Calendar/Alarm with EEPROM |
| X1243S8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Real Time Clock/Calendar/Alarm with EEPROM |
| X1243S8I | 制造商:Intersil Corporation 功能描述: 制造商:XICOR 功能描述: |
| X1243V8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Real Time Clock/Calendar/Alarm with EEPROM |
| X-1244 | 制造商:Pulse 功能描述:TRANSFORMERS - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。