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參數(shù)資料
| 型號： | X1242S8 |
| 英文描述： | 200V Single N-Channel HEXFET Power MOSFET in a SO-8 package; A IRF7450 with Standard Packaging |
| 中文描述： | 集成電路表面貼裝與EEPROM的時鐘 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 119K |
| 代理商： | X1242S8 |
X1242 – Preliminary Information
Characteristics subject to change without notice.
11 of 24
REV 1.1.3 10/15/00
www.xicor.com
Figure 13. Byte Write Sequence
Figure 14. Writing
30
-bytes to a
64
-byte memory page starting at address
40
.
S
t
a
r
t
S
t
o
p
Slave
Address
Word
Address 1
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals From
The Slave
Signals from
the Master
0
A
C
K
Word
Address 0
1
1
1
1
0 0 00 0
Address
63
Address
40
23 Bytes
7 Bytes
Address
= 6
Address Pointer
Ends Here
Addr =
7
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1242 will not initiate an internal
write cycle, and will continue to ACK commands.
Page Write
The X1242 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first
data byte is transferred, the master can transmit up to
63
more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (
Note:
Prior to writ-
ing to the CCR, the master must write a 02h, then 06h
to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/
Control Registers” on page 6.)
After the receipt of each byte, the X1242 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. If the master begins writing at location 40 of the
memory and loads 30 bytes, then the first 23 bytes are
written to addresses 40 through 63, and the last 7
bytes are written to columns 0 through 6. Afterwards,
the address counter would point to location 7 on the
page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over written by the new data, one byte
at a time.
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the X1242 to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 15 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1242 resets itself without per-
forming the write. The contents of the array are not
affected.
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PDF描述 |
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| X1242 | Real Time Clock/Calendar/Alarms/CPU Supervisor(實時時鐘/日歷/鬧鐘/帶EEPROM的監(jiān)控) |
| x1243(中文) | Real Time Clock/Calendar/Alarm with EEPROM(帶EEPROM的實時時鐘/日歷/鬧鐘) |
| X12xx-EVM(中文) | Xicor RTC X12xx-EVM User Guide(XICOR RTC X12xx-EVM評估板使用說明) |
| X187 | TEMPERATURSICHERUNG 187GRAD 5ST |
| X25 | 40V Single N-Channel HEXFET Power MOSFET in a D2-Pak package; A IRL1004S with Standard Packaging |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X1243 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock/Calendar/Alarm with EEPROM |
| X1243S8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Real Time Clock/Calendar/Alarm with EEPROM |
| X1243S8I | 制造商:Intersil Corporation 功能描述: 制造商:XICOR 功能描述: |
| X1243V8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Real Time Clock/Calendar/Alarm with EEPROM |
| X-1244 | 制造商:Pulse 功能描述:TRANSFORMERS - Rail/Tube |
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