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參數(shù)資料
| 型號(hào)： | X1205V8Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2-Wire RTC Real Time Clock/Calendar |
| 中文描述： | REAL TIME CLOCK, PDSO8 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 407K |
| 代理商： | X1205V8Z |
Figure 7. Byte Write Sequence
X1205 – Preliminary Information
REV 1.0.9 8/29/02
Characteristics subject to change without notice.
9 of 22
www.xicor.com
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0H,
so a current address read of the CCR array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 6.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. For a random read of the Clock/Control
Registers, the slave byte must be 1101111x in both
places.
Figure 6. Slave Address, Word Address, and Data Bytes
Slave Address Byte
Byte 0
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
Data Byte
Byte 3
A6
A5
0
0
0
0
0
0
0
1
1
0
1
1
1
R/W
1
0
Word Address 1
Byte 1
Word Address 0
Byte 2
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the CCR.
(Note: Prior to writing to the CCR, the master must
write a 02h, then 06h to the status register in two pre-
ceding operations to enable the write operation. See
“Writing to the Clock/Control Registers.” Upon receipt
of each address byte, the X1205 responds with an
acknowledge. After receiving both address bytes the
X1205 awaits the eight bits of data. After receiving the
8 data bits, the X1205 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1205 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 7.
S
t
a
r
t
S
t
o
p
Slave
Address
Word
Address 1
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals From
The Slave
Signals from
the Master
0
A
C
K
Word
Address 0
1
1
1
1
0 0 0 0 0 0 0 0
1 0 1
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