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參數資料
| 型號： | X1205V8Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2-Wire RTC Real Time Clock/Calendar |
| 中文描述： | REAL TIME CLOCK, PDSO8 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8 |
| 文件頁數： | 4/22頁 |
| 文件大?。?/td> | 407K |
| 代理商： | X1205V8Z |
MNA1
EMN1
A1M22
A1M21
A1M20
SCA1
ESC1
A1S22
A1S21
A1S20
Alarm0
(NONVOLATILE)
DWA0
EDW0
0
0
YRA0
Unused – Default = RTC Year value – Future expansion
MOA0
EMO0
0
0
DTA0
EDT0
0
A0D21
HRA0
EHR0
0
A0H21
MNA0
EMN0
A0M22
A0M21
SCA0
ESC0
A0S22
A0S21
X1205 – Preliminary Information
REV 1.0.9 8/29/02
Characteristics subject to change without notice.
4 of 22
www.xicor.com
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
Bit
Range
D
7
6
5
4
3
2
1
0
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Status
SR
Y2K
DW
YR
MO
DT
HR
SC
DTR
ATR
INT
0
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
BAT
0
0
Y23
0
0
MIL
0
0
0
0
IM
0
0
EDW1
AL1
0
0
Y22
0
0
0
M22
S22
0
0
AL1E
0
0
0
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
ATR5
AL0E
0
A1Y2K21
0
Unused – Default = RTC Year value – Future expansion
0
A1G20
A1D21
A1D20
A1H21
A1H20
0
0
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
X
0
0
DY2
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
X
0
0
DY1
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
X
0
A1Y2K10
DY0
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
20h
00h
RTC (SRAM)
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
ATR4
0
0
A1Y2K20
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
0
0
A1Y2K13
0
0-6
0-99
1-12
1-31
0-23
0-59
0-59
Control
(NONVOLATILE)
Alarm1
(NONVOLATILE)
0-6
EMO1
EDT1
EHR1
0
0
0
A1G13
A1D13
A1H13
A1M13
A1S13
A0Y2K13
0
A1G12
A1D12
A1H12
A1M12
A1S12
0
DY2
A1G11
A1D11
A1H11
A1M11
A1S11
0
DY1
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
1-12
1-31
0-23
0-59
0-59
19/20
0-6
00h
00h
00h
00h
00h
20h
00h
Y2K0
0
0
A0Y2K21
A0Y2K20
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
– Setting the Enable Month Bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1205 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00AM
Wednesday.
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30PM.
*n = 0 for Alarm 0: N = 1 for Alarm 1
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相關代理商/技術參數 |
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