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參數(shù)資料
| 型號(hào)： | WV3HG32M72EER403AD6SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 180K |
| 代理商： | WV3HG32M72EER403AD6SG |
8
WV3HG32M72EER-AD6
September 2005
Rev. 1
PRELIMINARY
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS (continued)
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
534
403
Unit
Min
Max
Min
Max
Command
and
Address
Address and control input pulse width for each input
tIPW
0.6
tCK
Address and control input setup time
tIS
250
ps
Address and control input hold time
tIH
375
475
ps
CAS# to CAS# command delay
tCCD
22
ps
ACTIVE to ACTIVE (same bank) command
tRC
60
65
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
15
ns
Four Bank Activate period
tFAW
37.5
ns
ACTIVE to PRECHARGE command
tRAS
45
70,000
45
70,000
ns
Internal READ to precharge command delay
tRTP
7.5
ns
Write recovery time
tWR
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR + tRP
ns
Internal WRITE to READ command delay
tWTR
7.5
10
ns
PRECHARGE command period
tRP
15
ns
PRECHARGE ALL command period
tRPA
tRP + tCK
ns
LOAD MODE command cycle time
tMRD
22
tCK
CKE low to CK, CK# uncertainty
tDELAY
4.375
ns
Self
Refresh
REFRESH to Active or Refresh to Refresh command interval
tRFC
127.5
70,000
127.5
70,000
ns
Average periodic refresh interval
tREFI
7.8
ns
Exit self refresh to non-READ command
tXSNR
tRPC(MIN) + 10
tRFC(MIN) + 10
ns
Exit self refresh to READ
tXSRD
200
tCK
Exit self refresh timing reference
tlSXR
tIS
ps
ODT
ODT tum-on delay
tAOND
2222
tCK
ODT turn-on
tACN
tAC(MIN)
tAC(MAX) +
1000
tAC(MIN)
tAC(MAX) +
1000
ps
ODT turn-off delay
tAOFD
2.5
tCK
ODT tum-off
tAOF
tAC(MIN)
tAC(MAX) +
600
tAC(MIN)
tAC(MAX) +
600
ps
ODT tum-on (power-down mode)
tAONPD
tAC(MIN) +
2000
2 x tCK +
tAC(MAX) +
1000 +1000
tAC(MIN) +
2000
2 x tCK +
tAC(MAX) +
1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC(MIN) +
2000
2 x tCK +
tAC(MAX) +
1000 +1000
tAC(MIN) +
2000
2 x tCK +
tAC(MAX) +
1000
ps
ODT to power-down entry latency
tANPD
33
tCK
ODT power-down exit latency
tAXPD
88
tCK
Power-Down
Exit active power-down to READ command, MR[bit12=0]
tXARD
22
tCK
Exit active power-down to READ command, MR[bit12=1]
tXARDS
6-AL
tCK
Exit precharge power-down to any non-READ command
tXP
22
tCK
CKE minimum high/low time
tCKE
33
tCK
IDD specication is based on SAMSUNG components. Other DRAM manufacturers specication may be different.
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