參數(shù)資料
型號(hào): WV3EG64M64ETSU403D4IMG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 64M X 64 DDR DRAM MODULE, 0.65 ns, ZMA200
封裝: ROHS COMPLIANT, SODIMM-200
文件頁數(shù): 12/12頁
文件大?。?/td> 177K
代理商: WV3EG64M64ETSU403D4IMG
WV3EG64M64ETSU-D4
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C
AC Characteristics
403
335
Units
Parameter
Symbol
Min
Max
Min
Max
DQS-in high level width
tDQSH
0.35
tCK
DQS-in low level width
tDQSL
0.35
tCK
Address and control input setup time (fast)
tISF
0.6
0.75
ns
Address and control input hold time (fast)
tIHF
0.6
0.75
ns
Address and control input setup time (slow)
tISs
0.7
0.8
ns
Address and control input hold time (slow)
tIHS
0.7
0.8
ns
Data-out high-impedance time from CK/CK#
tHZ
+0.65
+0.70
ns
Data-out low-impedance time from CK/CK#
tLZ
-0.65
-0.70
ns
Mode register set cycle
tMRD
10
12
ns
DQ and DM input setup time to DQS
tDS
0.4
0.45
ns
DQ and DM input hold time to DQS
tDH
0.4
0.45
ns
Control & address input pulse width
tIPW
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
ns
Exit self refresh to non-Read command
tXSNR
75
ns
Exit self refresh to Read command
tXSRD
200
tCK
Refresh interval time
tREFI
7.8
s
Output DQS valid window
tQH
tHP - tQHS
ns
Clock Half period
tHP
tCL(MIN) or tCH(MAX)
ns
Data hold skew factor
tQHS
0.5
ns
DQS write postable
tWPST
0.4
0.6
0.4
0.6
ns
Active read with auto precharge command
tRAP
15
18
ns
Auto precharge write recovery + precharge time
tDAL
tWR/tCK
+
tRP/tCK
tWR/tCK
+
tRP/tCK
tCK
Notes:
Industrial grade modules are specied to a DRAM tCASE of 85°C and -40°C
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