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參數(shù)資料
| 型號(hào)： | WV3DG64127V10D2 |
| 英文描述： | 1GB - 2x64Mx64, SDRAM UNBUFFERED |
| 中文描述： | 1GB的- 2x64Mx64，內(nèi)存緩沖 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 255K |
| 代理商： | WV3DG64127V10D2 |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WV3DG64127V-D2
April 2005
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
ADVANCED*
OPERATING AC PARAMETERS
V
CC
, V
CCQ
= +3.3v ±0.3V, 0°C - 70°C
Parameter
Symbol
7
75
10
Unit
Note
Min
7.5
7.5
Max
Min
7.5
10
Max
Min
10
10
Max
CLK cycle time
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
t
CC
1000
1000
1000
ns
1
CLK to valid output delay
t
SAC
5.4
5.4
5.4
6
6
6
ns
1, 2
Output data hold time
t
OH
3
3
3
3
3
3
3
3
2
1
1
ns
2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
t
CH
t
CL
t
SS
t
SH
t
SLZ
2.5
2.5
1.5
0.8
1
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
ns
3
3
3
3
2
CLK to outpu in Hi-Z
CAS latency=3
CAS latency=2
t
SHZ
5.4
5.4
5.4
6
6
6
Notes :
1.
2.
3.
Parameters depend on programmed CAS latency.
If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3DG64127V75D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64, SDRAM UNBUFFERED |
| WV3DG64127V7D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64, SDRAM UNBUFFERED |
| WV3DG64127V-D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64, SDRAM UNBUFFERED |
| WV3DG72256V-AD2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 SDRAM, REGISTERED |
| WV3DG7266V10D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
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