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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
WSF512K16-XXX
512K
X
16 SRAM/FLASH MODULE, SMD 5962-96901
FEATURES
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Access Times of 35ns (SRAM) and 90ns (FLASH)
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Access Times of 70ns (SRAM) and 120ns (FLASH)
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Packaging
66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic
HIP (Package 402)
68 lead, Hermetic CQFP (G2), 22mm (0.880") square
(Package 500). Designed to fit JEDEC 68 lead 0.990” CQFJ
footprint (Fig. 2)
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512Kx16 SRAM
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512Kx16 5V FLASH
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Organized as 512Kx16 of SRAM and 512Kx16 of Flash
Memory with separate Data Busses
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Both blocks of memory are User Configurable as 1Mx8
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Low Power CMOS
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Commercial, Industrial and Military Temperature Ranges
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TTL Compatible Inputs and Outputs
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Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
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Weight - 13 grams typical
FIG. 1
PIN CONFIGURATION FOR WSF512K16-XH2X
TOP VIEW
FWE FCS
FWE FCS
SWE SCS
2
512K x 8
SRAM
8
SD
0-7
1
1
512K x 8
SRAM
8
SD
8-15
2
512K x 8
FLASH
8
FD
0-7
1
512K x 8
FLASH
8
FD
8-15
2
A
0
-
18
OE
SWE SCS
PIN DESCRIPTION
FD
0-15
Flash Data Inputs/Outputs
SD
0-15
SRAM Data Inputs/Outputs
A
0-18
Address Inputs
SWE
1-2
SRAM Write Enable
SCS
1-2
SRAM Chip Selects
OE
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
FWE
1-2
Flash Write Enable
FCS
1-2
Flash Chip Select
SD
8
SD
9
SD
10
A
13
A
14
A
15
A
16
A
18
SD
0
SD
1
SD
2
SWE
2
SCS
2
GND
SD
11
A
10
A
11
A
12
V
CC
SCS
1
NC
SD
3
SD
15
SD
14
SD
13
SD
12
OE
A
17
SWE
1
SD
7
SD
6
SD
5
SD
4
FD
8
FD
9
FD
10
A
6
A
7
NC
A
8
A
9
FD
0
FD
1
FD
2
V
CC
FCS
2
FWE
2
FD
11
A
3
A
4
A
5
FWE
1
FCS
1
GND
FD
3
FD
15
FD
14
FD
13
FD
12
A
0
A
1
A
2
FD
7
FD
6
FD
5
FD
4
11 22 33 44 55 66
1 12 23 34 45 56
FLASH MEMORY FEATURES
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100,000 Erase/Program Cycles
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Sector Architecture
8 equal size sectors of 64K bytes each
Any combination of sectors can be concurrently erased.
Also supports full chip erase
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5 Volt Programming; 5V
±
10% Supply
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Embedded Erase and Program Algorithms
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Hardware Write Protection
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Page Program Operation and Internal Program Control Time.
Note: Programming information available upon request.
October 2000 Rev.
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BLOCK DIAGRAM