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參數(shù)資料
| 型號(hào)： | WM8782 |
| 廠商： | Wolfson Microelectronics |
| 元件分類(lèi)： | ADC |
| 英文描述： | 24-Bit, 192kHz Stereo ADC |
| 中文描述： | 24位192kHz立體聲ADC |
| 文件頁(yè)數(shù)： | 13/19頁(yè) |
| 文件大?。?/td> | 216K |
| 代理商： | WM8782 |
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WM8782
w
PP, May 2004, Rev 1.0
13
MASTER CLOCK AND AUDIO SAMPLE RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock (MCLK). The external master system clock can be applied directly through the MCLK
input pin. In a system where there are a number of possible sources for the reference clock it is
recommended that the clock source with the lowest jitter be used to optimise the performance of the
ADC.
The master clock is used to operate the digital filters and the noise shaping circuits. The WM8782
supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio
sampling frequency (LRCLK). In Slave Mode, the WM8782 automatically detects the audio sample
rate. In Master Mode, LRCLK is generated for rate 256fs, unless the user changes this to 128fs
using the FSAMPEN pin = z (see Table 7 below). BCLK is also generated in Master Mode.
BCLK=MCLK/4 for 256fs, and BCLK=MCLK/2 for 128fs.
Table 6 shows the common MCLK frequencies for different sample rates.
Master Clock Frequency (MHz)
SAMPLING RATE
(LRCLK)
128fs
192fs
256fs
384fs
512fs
768fs
8kHz
16kHz
32kHz
44.1kHz
48kHz
96kHz
192kHz
1.024
2.048
4.096
5.6448
6.144
12.288
24.576
1.536
3.072
6.144
8.467
9.216
18.432
36.864
2.048
4.096
8.192
11.2896
12.288
24.576
-
3.072
6.144
12.288
16.9340 22.5792 33.8688
18.432
24.576
36.864
-
-
-
4.096
8.192
16.384
6.144
12.288
24.576
36.864
-
-
Table 6 Master Clock Frequency Selection
In Slave mode, the WM8782 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available
(768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8782 is tolerant of
phase variations or jitter on these clocks.
The WM8782 can operate at sample rates from 8kHz to 192kHz. The WM8782 uses a sigma-delta
modulator that operates at a fixed frequency of 6.144MHz (128 x LRCLK oversampling @ 48kHz
sampling rate). For correct operation of the device and optimal performance, the user must set the
appropriate ADC modulator sampling rate enable. In both Master and Slave Modes, it is
recommended that for 96kHz the user sets FSAMPEN to 1, and for 192kHz set FSAMPEN to z. For
Master Mode 192kHz, FSAMPEN set to z is a requirement.
PIN
DESCRIPTION
M/S
Master/Slave Selection
0 = Slave Mode (128fs, 192fs,
256fs, 384fs, 512fs, 768fs)
1= Master Mode (256fs, 128fs
when FSAMPEN=z)
Fast sampling rate enable
0 = 48ken (128x OSR)
1= 96ken (64x OSR)
z= 192ken (32x OSR)
FSAMPEN
Table 7 Master/Slave and sampling rate enable selection
POWER DOWN CONTROL
The WM8782 can be powered down by stopping MCLK. Power down mode using MCLK is entered
after 65536/fs clocks. On power-up, the WM8782 applies the power-on reset sequence described
below.
When MCLK is stopped DOUT is forced to zero.
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相關(guān)代理商/技術(shù)參數(shù) |
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| WM8782_06 | 制造商:WOLFSON 制造商全稱(chēng):WOLFSON 功能描述:24-Bit, 192kHz Stereo ADC |
| WM8782_10 | 制造商:WOLFSON 制造商全稱(chēng):WOLFSON 功能描述:24-Bit, 192kHz Stereo ADC |
| WM8782-6125-SSOP20-EV1 | 制造商:Wolfson Microelectronics 功能描述:Evaluation Board for WM8782 Stereo ADC |
| WM8782ASEDS/RV | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC STEREO ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
| WM8782ASEDS/V | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC STEREO ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
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