參數(shù)資料
型號: WM8718SEDS
廠商: Wolfson Microelectronics
英文描述: 24 BIT DIFFERENTIAL STEREO DAC WITH VOLUME CONTROL
中文描述: 24位差分立體聲DAC,具有音量控制
文件頁數(shù): 18/27頁
文件大?。?/td> 284K
代理商: WM8718SEDS
WM8718
Production Data
w
PD Rev 4.1 March 2004
18
ZERO FLAG OUTPUTS
The WM8718 has two zero flag outputs pins. The WM8718 asserts a low on the corresponding
zero flag pin when a sequence of more than 1024 mid-rail signal is input to the chip. The user
can use the zero flag pins to control external muting circuits if required. To simplify external
circuitry there is an option to have both zero flag output’s ANDed internally and output on both
pins.
REGISTER
ADDRESS
0010
Mode
Control
BIT
LABEL
DEFAULT
DESCRIPTION
7
ZEROFLR
0
ZERO Flag Outputs:
0: Both pins enabled.
1: AND of both channels to both pins.
ZERO CROSS DETECT
When the WM8718 receives updates to the volume levels it will, by default, wait for the signal to
pass through mid-rail for each channel before applying the update for that particular channel. This
ensures that there is minimum distortion seen on the output when the volume is changed.
REGISTER ADDRESS
0010
Mode Control
BIT
8
LABEL
ZCDINIT
DEFAULT
0
DESCRIPTION
Zero Cross Detect Control:
0: Enabled
1: Disabled
SELECTION OF LRCIN POLARITY
In left justified, right justified or I
2
S modes, the LRP register bit controls the polarity of LRCIN. If
this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 4,
Figure 5 and Figure 6. Note that if this feature is used as a means of swapping the left and right
channels, a 1 sample phase difference will be introduced.
REGISTER ADDRESS
0011
Format Control
BIT
4
LABEL
LRP
DEFAULT
0
DESCRIPTION
LRCIN Polarity (normal)
0: normal LRCIN polarity
1: inverted LRCIN polarity
Table 6 LRCIN Polarity Control
In DSP modes, the LRCIN register bit is used to select between early and late modes (see Figure
7 and Figure 8.
REGISTER ADDRESS
0011
Format Control
BIT
4
LABEL
LRP
DEFAULT
0
DESCRIPTION
DSP Format (DSP modes)
0: Late DSP mode
1: Early DSP mode
Table 7 DSP Format Control
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the
BCKIN rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed
between the data words. The word order is DIN left, DIN right.
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