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參數(shù)資料
| 型號： | WM8190 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | TVS UNIDIRECT 6V 400W SMA |
| 中文描述： | （8 6）位輸出14位獨聯(lián)體/防治荒漠化公約AFE的/數(shù)字轉換器 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 438K |
| 代理商： | WM8190 |
WM8190
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 August 1999
16
EN
0
1
X
SELDPD
0
0
1
Device completely powers down.
Device completely powers up.
Blocks with respective SELDIS[3:0] bit high are disabled.
Table 3 Power Down Control
LINE-BY-LINE OPERATION
Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to
accommodate this type of signal the WM8190 can be set into Monochrome mode, with the input
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8190
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is
set the green and blue processing channels are powered down and the device is forced internally to
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.
Figure 16 shows the signal path when operating in colour line-by-line mode.
RINP
SEN
SCK
VSMP
MCLK
VRLC/VBIAS
SDI
RLC/ACYC
RLC
BINP
GINP
INPUT
MUX
OFFSET
MUX
RLC
R
G
B
R
G
B
PGA
I/P SIGNAL
POLARITY
ADJUST
8
RLC
DAC
+
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
OP[7:0]
+
WM8190
14-
BIT
ADC
DATA
I/O
PORT
8
OFFSET
DAC
PGA
MUX
TIMING CONTROL
CL
V
S
R
S
4
CDS
RLC
Figure 16 Signal Path When in Line-by-Line Mode
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.
The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively,
all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to
select the desired colour. It is also possible for the input multiplexer to be controlled separately from
the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are
possible.
FME
0
ACYCNRLC
0
NAME
DESCRIPTION
Internal,
no force mux
Auto-cycling,
no force mux
Internal,
force mux
Input mux, offset and gain registers determined by
internal register bits INTM1, INTM0.
Input mux, offset and gain registers auto-cycled, RINP
→
GINP
→
BINP
→
RINP… on RLC/ACYC pulse.
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers selected from internal register
bits INTM1, INTM0.
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers auto-cycled, RINP
→
GINP
→
BINP
→
RINP… on RLC/ACYC pulse.
0
1
1
0
1
1
Auto-cycling,
force mux
Table 4 Colour Selection Description in Line-by-Line Mode
相關PDF資料 |
PDF描述 |
|---|---|
| WM8191 | TVS BI-DIR 6.0V 400W SMA |
| WM8192 | TVS UNIDIRECT 400W 6.5V SMA |
| WM8196 | (8+8)BIT OUTPUT 16-BIT CIS/CCD AFE/DIGITISER |
| WM8199 | 20MSPS 16-bit CCD Digitiser |
| WM8199CDR | TVS BIDIRECT 400W 60V SMA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WM8191 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:14-bit 6MSPS CIS/CCD Analogue Front End/Digitiser |
| WM8192 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:(8+8) Bit Output 16-bit CIS/CCD AFE/Digitiser |
| WM8195 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser |
| WM8195_05 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser |
| WM8195SCFT/RV | 功能描述:模數(shù)轉換器 - ADC 14Bit 12MSPS 3C AFE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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