參數(shù)資料
型號(hào)： WM8190
廠商： Wolfson Microelectronics
英文描述： TVS UNIDIRECT 6V 400W SMA
中文描述： （8 6）位輸出14位獨(dú)聯(lián)體/防治荒漠化公約AFE的/數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 14/25頁(yè)
文件大?。?/td> 438K
代理商： WM8190
WM8190
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 August 1999
14
CONTROL INTERFACE
The internal control registers are programmable via the serial digital control interface. The register
contents can be read back via the serial interface on pin OP[7]/SDO.
SERIAL INTERFACE: REGISTER WRITE
Figure 13 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data
word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK.
When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the
appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
SEN
SDI
a5
0
a3
Address
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
Data Word
Figure 13 Serial Interface Register Write
SERIAL INTERFACE: REGISTER READ-BACK
Figure 14 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge
of SCK). Note that pin SDO is shared with an output pin, OP[7], therefore OEB should always be
held low when register read-back data is expected on this pin. The next word may be read in to SDI
while the previous word is still being output on SDO.
SCK
SEN
SDI
a5
1
a3 a2
Address
a1 a0
x
x
x
x
x
x
x
x
Data Word
d7 d6 d5 d4
Output Data Word
d3 d2 d1 d0
SDO/
OP[7]
OEB
Figure 14 Serial Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock
(VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum
sample rates for the various modes are shown in Table 5.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
WM8191 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:14-bit 6MSPS CIS/CCD Analogue Front End/Digitiser
WM8192 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:(8+8) Bit Output 16-bit CIS/CCD AFE/Digitiser
WM8195 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
WM8195_05 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
WM8195SCFT/RV 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14Bit 12MSPS 3C AFE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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