參數(shù)資料
型號(hào): WM2633
廠(chǎng)商: Wolfson Microelectronics
英文描述: BOX 6.88X4.88X1.51 9V GRY
中文描述: 字節(jié)寬并行輸入,12位電壓輸出DAC,帶有內(nèi)部參考
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 389K
代理商: WM2633
WM2633
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999
6
8.
I
DD
is measured while continuously writing code 2048 to the DAC. For V
IH
< DVDD - 0.7V and V
IL
> 0.7V
supply current will increase.
9.
Typical supply current
in powerdown mode is 10nA. Production test limits are wider for speed of test.
10.
Slew rate results
are for the lower value of the rising and falling edge slew rates.
11.
Settling time
is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
12
. SNR, SNRD, THD
and
SPFDR
are measured on a synthesised sinewave at frequency f
OUT
generated with
a sampling frequency f
S
.
PARALLEL INTERFACE
D[0-7]
A[0-1]
NCS
NWE
NLDAC
Data
X
X
Address
X
X
t
SUD
t
HD
t
SUA
t
SUCSWE
t
WWE
t
SUWELD
t
WLD
t
HA
Figure 1 Timing Diagram
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
t
SUCSWE
Setup time NCS low before positive NWE edge
15
ns
t
SUD
Data ready before positive NWE edge
10
ns
t
HD
Data hold after positive NWE edge
5
ns
t
SUA
Setup time for address bits A0, A1
20
ns
t
SUWELD
Positive NWE edge before NLDAC low
5
ns
t
WWE
High pulse width of NWE
20
ns
t
WLD
Low pulse width of NLDAC
23
ns
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