參數(shù)資料
型號: WM2633
廠商: Wolfson Microelectronics
英文描述: BOX 6.88X4.88X1.51 9V GRY
中文描述: 字節(jié)寬并行輸入,12位電壓輸出DAC,帶有內(nèi)部參考
文件頁數(shù): 10/12頁
文件大?。?/td> 389K
代理商: WM2633
WM2633
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999
10
SOFTWARE CONFIGURATION OPTIONS
DATA FORMAT
The WM2613 writes data either to one of the DAC holding latches or to the control register
depending on the address bits A1 and A0.
A1
0
0
1
1
A0
0
1
0
1
LATCH
D7
D6
D5
D4
D3
D2
D1
D0
DAC LSW holding
DAC MSW holding
Reserved
Control
DAC 7
X
0
X
DAC 6
X
0
X
DAC 5
X
0
X
DAC 4
X
0
REF1
DAC 3
DAC 11
0
REF0
DAC2
DAC 10
0
RLDAC
DAC 1
DAC 9
0
PWR
DAC 0
DAC 8
0
SPD
Table 2 Register Map
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 3.5
μ
s or 1
μ
s, typical to within
±
0.5LSB of final value. This is
controlled by the value of SPD
Bit D12. A ONE defines a settling time of 1
μ
s, a ZERO defines a
settling time of 3.5
μ
s.
PIN
SPD
0
0
1
1
BIT
SPD
0
1
0
1
MODE
Slow
Fast
Fast
Fast
Table 3 Programmable Settling Time
PROGRAMMABLE POWER DOWN
The power down function can be controlled by PWR. A ZERO configures the device as active, or fully
powered up, a ONE configures the device into power down mode. When the power down function is
released the device reverts to the DAC code set prior to power down.
PIN
NPD
0
0
1
1
BIT
PWD
0
1
0
1
POWER
Down
Down
Normal
Down
Table 4 Programmable Power Down
LOAD DAC LATCH
Bit RLDAC controls the function of the DAC latch. A ONE configures the DAC latch as transparent. A
ZERO configures the DAC latch to be controlled by pin NLDAC.
PIN
BIT
NLDAC
0
0
1
1
RLDAC
0
1
0
1
LATCH
Transparent
Transparent
Hold
Transparent
Table 5 Load DAC Latch
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