參數(shù)資料
型號: WM2626ID
廠商: Wolfson Microelectronics
英文描述: Low Power Dual 8-bit Serial Input DAC with Internal Reference
中文描述: 低功耗雙8位串行輸入DAC的內(nèi)部參考
文件頁數(shù): 7/11頁
文件大?。?/td> 109K
代理商: WM2626ID
Production Data
WM2626
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
7
DEVICE DESCRIPTION
GENERAL FUNCTION
The WM2626 is a dual 8-bit, voltage output DAC with an on-chip voltage reference. It uses a
resistor string network buffered with an op amp to convert 8-bit digital data to analogue voltage
levels (see Block Diagram). The output voltage is determined by the reference voltage and the
input code according to the following relationship:
(
)
256
2
CODE
V
out
V
REFIN
=
INPUT
OUTPUT
(
V
1111
1111
)
256
255
2
REF
:
:
1000
0001
(
)
256
129
2
REF
V
1000
0000
(
)
REF
REF
V
V
=
256
128
2
0111
1111
(
)
256
127
2
REF
V
:
:
0000
0001
(
)
256
1
2
REF
V
0000
0000
0V
Table 1 Binary Code Table (0V to 2V
REF
Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2k
load with a 100pF load capacitance.
SERIAL INTERFACE
Before writing any data to the WM2626, the interface must be enabled by setting NCS to low.
Incoming data on DIN (starting with the MSB) is then shifted bit-per-bit into the internal register on
the falling edges of SCLK. From there data is loaded into the target latch after 16 bits have been
transferred, or when NCS rises. Four internal latches can be addressed: DAC A, DAC B, the buffer
latch or the control register. Their function is explained below (see
Register Addressing
).
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
MHz
t
t
f
WL
WH
SCLK
20
1
+
min
min
max
=
=
Since a data word contains 16 bits, the sample rate for one channel is limited to
(
)
MHz
t
t
f
WL
WH
s
25
.
16
1
min
min
max
=
+
×
=
For full two-channel operation, where two data words need to be transmitted per sample, this figure
is halved to 625kHz. However, the DAC settling time to 8-bit accuracy limits the response time of
the analogue output for large input step transitions.
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