參數(shù)資料
型號： WEDPNF8M721V-1015BM
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁數(shù)： 13/42頁
文件大小： 1297K
代理商： WEDPNF8M721V-1015BM
20
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
power-down. The command register and all internal program/
erase circuits are disabled, and the device resets. Subsequent
writes are ignored until Vcc is greater than VLKO. The system
must provide the proper signals to the control pins to prevent
unintentional writes when Vcc is greater than VLKO.
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5ns (typical) on FOE, FCS, or FWE
do not initiate a write cycle.
LOGICAL INHIBIT
Write cycles are inhibited by holding any one of FOE = VIL,
FCS = VIH or FWE = VIH. To initiate a write cycle, FCS and
FWE must be a logical zero while FOE is a logical one.
POWER-UP WRITE INHIBIT
If FWE = FCS = VIL and FOE = VIH during power up, the
device does not accept commands on the rising edge of
FWE. The internal state machine is automatically reset to read-
ing array data on power-up.
FLASH COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. Table
7 defines the valid register command sequences.
Writing
incorrect address and data values or writing them in
improper sequence will reset the device to the read
array data.
All addresses are latched on falling edge of FWE or FCS,
whichever occurs later. All data is latched on the rising edge
of FWE or FCS, whichever occurs first. Refer to the appropri-
ate timing diagrams in the “Flash AC Characteristics” section.
READ ARRAY DATA
Upon initial device power-up the device defaults to read
array data. No commands are required to retrieve data. The
device is also ready to read array data after it has completed
an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the
device enters the Erase Suspend mode. The system can
read array data using the standard read timings, except that
if it reads at an address within erase-suspend sectors, the
device outputs status data. After completing a program-
ming operation in the Erase Suspend mode, the system may
once again read array data with the same exception. See
“Erase Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system
must issue the reset command to re-enable the
device for reading array data if FD5 goes high, or while in the
autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” on the “Bus
Operations” section for more information. The Data Sheet
Read Operations table provides the read parameters, and the
Read Operations Timing Diagram shows the timing diagram.
RESET COMMAND
Writing the reset command to the device resets the device
to reading array data. Address bits are “don't care” for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing be-
gins. This resets the device to reading array data. Once era-
sure begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before program-
ming begins. This resets the device to reading array data
(also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in
autoselect mode, the reset command
must be written to
return to reading array data (also applies to autoselect dur-
ing Erase Suspend mode).
If FD5 goes high during a program or erase operation, writ-
ing the reset command returns the device to reading array
data (also applies during Erase Suspend).
UNLOCK BYPASS COMMAND SEQUENCE
The unlock bypass feature allows the system to program bytes
or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence
is initiated by first writing two unlock cycles. This is followed by
a third write cycle containing the unlock bypass command,
20h. The device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this se-
quence contains the unlock bypass program command, A0h;
the second cycle contains the program address and data.
Additional data is programmed in the same manner. This mode
dispenses with the initial two unlock cycles required in the
standard program command sequence, resulting in fast total
programming time. Table 7 shows the requirements for the
command sequence.
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