參數(shù)資料
型號(hào)： WEDPNF8M721V-1015BM
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 10/42頁(yè)
文件大?。?/td> 1297K
代理商： WEDPNF8M721V-1015BM
18
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
SECTOR PROTECTION/
UNPROTECTION
The hardware sector protection feature disables both pro-
gram and erase operations in any sector. The hardware sec-
tor unprotection feature re-enables both program and erase
operations in previously protected sectors.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
This operation requires VID on the RST pin only, and can be
implemented either in-system or via programming equip-
ment. Figure 5 shows the algorithms and the timing diagram
is shown in figure 18. This method uses standard micro-
processor bus cycle timing. For sector unprotect, all un-
protected sectors must first be protected prior to the first
sector unprotect write cycle.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sector groups to change data-in system. The Sec-
tor Unprotect mode is activated by setting the RST pin to
VID. During this mode, formerly protected sector can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the RST pin, all the previously
protected sector groups will be protected again. Figure 16
shows the algorithm and the timing diagram is shown in
Figure 17, for this feature.
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to Table 7 for command definitions).
In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which
might otherwise be caused by spurious system level sig-
nals during Vcc power-up and power-down transitions, or
from system noise.
LOW VCC WRITE INHIBIT
When Vcc is less than VLKO, the device does not accept any
write cycles. Ths protects data during Vcc power-up and
Description
FCS
FOE
FWE
FA18
-12 FA11-10
FA9
FA8-7
FA6
FA5-2
FA1
FA0
FD7-0
Sector Protection
L
H
SA
XVID
XL
X
H
L
Verificaton
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't Care
01h
(protected)
00h
(unprotected)
TABLE 6 - AUTOSELECT CODES (HIGH VOLTAGE METHOD)
RST is held at Vss ± 0.3V, the device draws CMOS standby
current (IFCC4). If RST is held at VIL but not within Vss ±
0.3V, the standby current will be greater.
The RST pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory, en-
abling the system to read the boot-up firmware from the
Flash memory.
If RST is asserted during a program or erase operation, RY/
BY1 pin remains “0” (busy) until the internal reset operation is
complete, which requires a time of tREADY (during Embed-
ded Algorithms). The system can thus monitor RY/BY1 to
determine whether the reset operationis complete. If RST is
asserted when a program or erase operation is not execut-
ing (RY/BY1 pin is “1”), the reset operation is completed within
a time of tREADY (not during Embedded Algorithms). The
system can read data tRH after the RST pin returns to VIH.
Refer to the Flash AC Characteristics and hardware reset tables
for RST parameters and to Figure 19 for the timing diagram.
AUTOSELECT MODE
The autoselect mode provides sector protection verifica-
tion, through identifier codes input codes output on FD7-
0. This mode is primarily intended for programming equip-
ment to automatically match a device to be programmed
with its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5V) on address in FA9. Address
pins FA6, FA1, and FA0 must be as shown in Table 6. In
addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order ad-
dress bits (see Table 5). Table 6 shows the remaining ad-
dress bits that are “don't care.” When all necessary bits have
been set as required, the programming equipment may then
read the corresponding identifier code on FD7-0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command regis-
ter, as shown in Table 7. This method does not require VID.
See “Command Definitions” for details on using the
autoselect mode.
相關(guān)PDF資料
PDF描述
WF2M32-120G4TI5 8M X 8 FLASH 5V PROM MODULE, 120 ns, QMA68
WS512K16-17FLI 512K X 16 MULTI DEVICE SRAM MODULE, 17 ns, CDFP44
WS512K16-35FLIA 512K X 16 MULTI DEVICE SRAM MODULE, 35 ns, CDFP44
WE512K16-140G4QA 512K X 16 EEPROM 5V MODULE, 140 ns, CQFP68
WS512K32NV-15G2UC 512K X 32 MULTI DEVICE SRAM MODULE, 15 ns, CQFP68
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
WEDPNF8M721V-1210BC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M721V-1210BI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M721V-1210BM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M721V-1212BC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M721V-1212BI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*