參數(shù)資料
型號: WED7P2G0ATA8004C25
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: PROM
英文描述: 128M X 16 FLASH 3V PROM CARD, 300 ns, UUC68
封裝: CARD-68
文件頁數(shù): 8/10頁
文件大小: 222K
代理商: WED7P2G0ATA8004C25
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED7PxxxATA80xxC25
July 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC CHARACTERISTICS (cont'd):
True IDE Mode I/O Input (Read) Timing Specication
Item
Symbol
IEEE Symbol
Min ns.
Max ns.
Data Delay after IORD
td(IORD)
tIGLQV
100
Data Hold following IORD
th(IORD)
tIGHQX
0
IORD Width Time
tw(IORD)
tIGLIGH
165
Address Setup before IORD
tsuA(IORD)
tAVIGL
70
Address Hold following IORD
thA(IORD)
tIGHAX
20
CE Setup before IORD
tsuCE(IORD)
tELIGL
5
CE Hold following IORD
thCE(IORD)
tIGHEH
20
I0IS16 Delay Falling from Address
tdfIOIS16(ADR)
tAVISL
35
I0IS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
Note: The maximum load on I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is 0 nsec, but minimum IORD# width
must still be met.
True IDE Mode I/O Output (Write) Timing Specication
Item
Symbol
IEEE Symbol
Min ns.
Max ns.
Data Setup before IOWR
tsu(IOWR)
tDVIWH
60
Data Hold following IOWR
th(IOWR)
tIWHDX
30
IOWR Width Time
tw(IOWR)
tIWLIWH
165
Address Setup before IOWR
tsuA(IOWR)
tAVIWL
70
Address Hold following IOWR
thA(IOWR)
tIWHAX
20
CE Setup before IOWR
tsuCE(IOWR)
tELIWL
5
CE Hold following IOWR
thCE(IOWR)
tIWHEH
20
I0IS16 Delay Falling from Address
tdfIOIS16(ADR)
tAVISL
35
I0IS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
Note: The maximum load on I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IOWR# high is 0 nsec, but minimum IOWR#
width must still be met.
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