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參數資料
| 型號： | WED3EL7216S7BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| 封裝： | BGA-219 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 1001K |
| 代理商： | WED3EL7216S7BC |
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WED3EL7216S
BGA LOCATIONS
SYMBOL
DESCRIPTION
F4, F16, G5, G15,
CKx, CKx\
Clock: CKx and CKx\ are differential clock inputs. All address and
K1, K12, L2, L13,
cont rol input signals are sampled on t he crossing of t he posit ive
N6, M8
edge o f CKx and negat ive edge of CKx\. Out put dat a ( DQ’ s and
DQS) is referenced to the crossings of the differential clock inputs
G4, G16, K2, K13
CKEx
Clock Enable: CKE cont rols t he clock input s. CKE high enables,
M6
CKE Low disables the clock input pins. Driving CKE Low pro-vides
PRECHARGE POWER-DOWN and SELF REFRESH
operations, or ACTIVE POWER-DOWN. CKE is synchronous
for POWER-DOWN ent ry and exit , and for SELF REFRESH ent ry
CKE is Asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read and
writ e accesses. Input buffers are disabled during POWER-DOWN
Input buffers are disabled during SELF REFRESH. CKE is an
SSTL-2 input but will det ect an LVCMOS LOW level aft er VCC
is applied
G1, G13, K4, K16
CSx\
Chip Select: CSx\ enagles t he COMMAND regist er(s) of each of
M12
t he five (5) cont ained words. All commands are masked when CSx\
is registered HIGH. CSx\ provides for external bank selection
on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
F4, F16, G5, G15,
RASx\, CASx\
Command Input s: RASx, CASx, and Wex\ define t he command
K1, K12, L2, L13,
WEx\
being ent ered
N7, M9
G4, G16, K2, K14
DQMLx, DQMHx
Input Data Mask. DM is an input mask signal for write data.
M7
Input dat a is masked when DQMLx or Hx is sampled HIGH at
t ime of a WRITE access. DM is sampled on bot h edges of DQSLx
and DQSHx
E8, E9
BA0, BA1
Bank Address Inputs: BA0, BA1 define which bank an ACTIVE
READ, WRITE, or PRECHARGE command is being applied
A7, A8, A9, A10, B7
A0-A11, A12
Address Input : Provide the row address for Active commands, and
B8, B9, B10, C7, C8
t he column address and aut o precharge bit (A10) for READ/WRITE
C9, C10, D7
commands to select one location out of the memory array int the
respective bank. A10 sampled during a PRECHARGE command
det ermines whether t he PRECHARGE applies t o one bank or
all banks. T he address input s also provide t he op-code during
a MODE RESI ST ER SE T c o mma n d.
PIN DESCRIPTIONS
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