- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄140344 > WED3EL7216S7BC (WHITE ELECTRONIC DESIGNS CORP) 16M X 72 DDR DRAM, 0.75 ns, PBGA219 PDF資料下載
參數(shù)資料
| 型號： | WED3EL7216S7BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| 封裝： | BGA-219 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 1001K |
| 代理商： | WED3EL7216S7BC |
2
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WED3EL7216S
PROGRAMMABLE IOH/IOL
The normal full drive strength for all outputs are specified to
be SSTL class 2. The WED3EL7216 suppor ts an option for
reduced drive. This option is intended for the suppor t of
the lighter load and or point-to-point environments. The
command and placement of this device into reduced drive
mode will place the output drive at ~54% of the SSTL-2.
DESELECT
The DESELECT command prevents new commands from
being executed by the WED3EL7216S devices.
NO OPERATION (NOP)
The NOP command is used to instruct the selected DDR
SDRAM device to perform idle or wait states. During these
states, the DDR SDRAM device is unable to register new
commands, operations already in progress are not affected.
The MODE REGISTERS are loaded via inputs A0-A11. The
LOAD MODE REGISTER command can only be issued when
all DDR SDRAM internal banks are idle.
LOAD MODE REGISTER
The ACTIVE command is used to open (or activate) a row
in a par ticular bank for a subsequent access. The value on
the BA0, BA1 inputs selects the bank, ant the address pro-
vided on inputs A0-A11 selects the row. The row remains
active for accesses until a PRECHARGE command is issued.
A PRECHARGE command must be issued before opening a
different row in the same bank.
ACTIVE
The READ command is used to initiate a BURST READ ac-
cess to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
Ax. Addressed location of the array will drive its contents
onto the DQ’s or the device
READ
The WRITE command is used to initiate a burst write. Input
data appearing on the DQ’s will be written into the address
location of the array.
WRITE
The PRECHARGE command is used to deactivate the open
row in a par ticular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a speci-
fied time (tRP) after the PRECHARGE command is issued.
PRECHARGE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WS128K32L-25G1TC | 128K X 32 MULTI DEVICE SRAM MODULE, 25 ns, CQFP68 |
| WS128K32L-35G1TC | 128K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CQFP68 |
| W3EG64129S262D3 | 128M X 64 DDR DRAM MODULE, DMA184 |
| WV3DG72256V75AD2SG | 256M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| W3DG7268V75AD1 | 64M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, ZMA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED416S16030A | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C10SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C75SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C7SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C8SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。