- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄140344 > WED3EL7216S7BC (WHITE ELECTRONIC DESIGNS CORP) 16M X 72 DDR DRAM, 0.75 ns, PBGA219 PDF資料下載
參數(shù)資料
| 型號： | WED3EL7216S7BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| 封裝： | BGA-219 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 1001K |
| 代理商： | WED3EL7216S7BC |
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WED3EL7216S
WED3EL7216S, DDR SR
WED3EL7216S, DDR SRAM, 2.5v CORE/ 2.5V IO
AM, 2.5v CORE/ 2.5V IO
March 2002 Rev. 1
Advanced*
FEATURES
INITIALIZATION
GENERAL DESCRIPTION
n Core Supply Voltage = 2.5v +/- 0.2v
n IO Supply Voltage = 2.5v +/- 0.2v
n Bidirectional data strobe (DQS)
n Internal, pipelined, double data rate architecture
n Differential Clock Inputs
n Positive edge; Command execution
n DLL for alignment of DQ and DQS transitions
n Four internal banks for concurrent operation
n Data Mask (DM) for masking write data
n Programmable IOL/IOH
n Programmable Burst length: 2,4, or 8
n Auto Precharge option
n Auto Refresh and Self Refresh Modes
The White Electronic Designs DDR SDRAM (x72/80) is a syn-
chronous dynamic random-access memory supporting data
transfer on each of the clock edges within a single cycle,
and is configured internally as a quad bank architecture
which suppor ts concurrent operations.
The double data rate (DDR) architecture is referenced to as
a 2n-pre-fetch architecture with an interface designed to
transfer two data words per clock cycle. A single Read or
Write access consists of a single 2n-bit wide, one clock
cycle data transfer at the internal DRAM core and two cor-
responding n-bit wide, one half clock cycle data transfers
at the I/O pins.
The WED3EL7216S devices contain differential clock inputs;
the crossing of CK going through its voltage transition to a
high true, and CK\ going through its voltage transition to a
low true references a positive edge. Commands as well as
Address(s) and Control(s) are registered on positive edges,
Data is registered on both edges as well as Output Data is
referenced on both edges of the Clock.
Read and Write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations, as defined by the
programmable burst command.
DDR SDRAMs must be initialized via properly powering up.
Operation and use of this device outside of established
procedure(s) may result in undefined operation. Power must
be first applied to Vcc and VccQ simultaneously and then
Vref (and System Vtt) must be applied after VccQ in order
to avoid device latch-up. Vref may be applied any time af-
ter VccQ but is normally expected at coincidence with Vtt.
Except for CKE (clock enable) inputs are not recognized
as valid until after Vref is applied. CKE is an SSTL_2 input but
will detect an LVCMOS Low level after Vcc is applied. Main-
taining an LVCOMOS Low level on CLE during power-up is
required to ensure that the DQ and DQS outputs will be in
the HIGH-Z state where they will remain until driven in a
normal READ operation. Once the POWER SUPPLY, and REF-
ERENCE VOLTAGE is STABLE, the DDR SDRAM device re-
quires 200us delay prior to execution of a COMMAND se-
quence. Once the 200us delay requirement has been meet,
a DESELECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a LOAD
MODE REGISTER command is to be issued for the extended
mode register (enabling the DLL) followed by another LOAD
MODE REGISTER command to be issued to reset the DLL
and program the operating parameters. Two hundred (200)
clock cycles are required between the DLL reset and any
READ command. A PRECHARGE ALL command should then
be applied, placing the device in the all banks idle state.
Once in the Idle state, two AUTO REFRESH cycles must be
performed. Additionally, a LOAD MODE REGISTER command
for the mode register with the reset DLL bit deactivated is
required. Following these requirements, the DDR SDRAM is
ready for NORMAL OPERATION.
相關PDF資料 |
PDF描述 |
|---|---|
| WS128K32L-25G1TC | 128K X 32 MULTI DEVICE SRAM MODULE, 25 ns, CQFP68 |
| WS128K32L-35G1TC | 128K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CQFP68 |
| W3EG64129S262D3 | 128M X 64 DDR DRAM MODULE, DMA184 |
| WV3DG72256V75AD2SG | 256M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| W3DG7268V75AD1 | 64M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, ZMA144 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WED416S16030A | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C10SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C75SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C7SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C8SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。