- 您現在的位置：買賣IC網 > PDF目錄140345 > WE32K32N-65H1IA (MICROSEMI CORP-PMG MICROELECTRONICS) 32K X 32 EEPROM 5V MODULE, 65 ns, CPGA66 PDF資料下載
參數資料
| 型號： | WE32K32N-65H1IA |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 32K X 32 EEPROM 5V MODULE, 65 ns, CPGA66 |
| 封裝： | 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66 |
| 文件頁數： | 8/13頁 |
| 文件大小： | 226K |
| 代理商： | WE32K32N-65H1IA |
4
White Microelectronics Phoenix, AZ (602) 437-1520
10
EEPROM
MODULES
A write cycle is initiated when OE is high and a low pulse is on
WE or CS with CS or WE low. The address is latched on the
falling edge of CS or WE whichever occurs last. The data is
latched by the rising edge of CS or WE, whichever occurs first.
A byte write operation will automatically continue to completion.
WE32K32-XXX
WRITE
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the CS line
low. Write enable consists of setting the WE line low. The
write cycle begins when the last of either CS or WE goes low.
The WE line transition from high to low also initiates an
internal 100
sec delay timer to permit page mode operation.
Each subsequent WE transition from high to low that occurs
before the completion of the 100
sec time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.
AC WRITE CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
WRITE CYCLE
Write Cycle Parameter
Symbol
Min
Typ(3)
Max
Unit
Write Cycle Time
tWC (1)
310
ms
Address Setup Time
tAS
0ns
Address Hold Time
tAH
50
ns
Write Setup Time
tCS
0ns
Write Hold Time
tCH
0ns
Write Pulse Width (WE or CS)
tWP
50
ns
OE High Setup Time
tOES
0ns
OE High Hold Time
tOEH
0ns
WE High Recovery
tWPH (2)
50
ns
(Page Write only)
Data Valid
tDV
1
s
Data Setup
tDS
50
ns
Data Hold
tDH
0ns
Delay to Next Write after Polling
tDW (2)
10
ns
is True
Byte Load Cycle
tBLC
0.15
100
ns
NOTES:
1. tWC is the minimum cycle time to be allowed from the system perspective
unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
2. tWPH and tDW are periodically sampled and not 100% tested.
3. Typical values are for TA = 25
°C and nominal supply voltage.
相關PDF資料 |
PDF描述 |
|---|---|
| WED3DG6418V7D2 | 16M X 64 SYNCHRONOUS DRAM MODULE, DMA168 |
| WF2M32-150HM5 | 2M X 32 FLASH 5V PROM MODULE, 150 ns, CPGA66 |
| WF2M32-90G2UQ5 | 2M X 32 FLASH 5V PROM MODULE, 90 ns, CQFP68 |
| WF2M32I-150G2UM5 | 2M X 32 FLASH 5V PROM MODULE, 150 ns, CQFP68 |
| WF2M32I-150HM5 | 2M X 32 FLASH 5V PROM MODULE, 150 ns, CPGA66 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| WE32K32N-80H1C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| WE32K32N-80H1CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| WE32K32N-80H1I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| WE32K32N-80H1IA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| WE32K32N-80H1M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復。