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參數(shù)資料
| 型號： | WE32K32N-65H1IA |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 32K X 32 EEPROM 5V MODULE, 65 ns, CPGA66 |
| 封裝： | 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 226K |
| 代理商： | WE32K32N-65H1IA |
White Microelectronics Phoenix, AZ (602) 437-1520
10
EEPROM
MODULES
7
WE32K32-XXX
READ
The WE32K32-XXX stores data at the memory location
determined by the address pins. When CS and OE are low and
WE is high, this data is present on the outputs. When CS and
OE are high, the outputs are in a high impedance state. This
two line control prevents bus contention.
AC READ CHARACTERISTICS
(See Figure 7)
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
FIG. 7
READ WAVEFORMS
NOTES:
1. OE may be delayed up to tACS - tOE after the falling edge of
CS without impact on tOE or by tACC - tOE after an address
change without impact on tACC.
2. tCHZ, tOHZ are specified from OE or CS whichever occurs
first (CL = 5pF).
3. All I/O transitions are measured
±200 mV from steady state
with loading as specified in "Load Test Circuits."
t
ADDRESS
CS
OE
OUTPUT
OH
tHZ& tOHZ
t ACC
t RC
t OE
tACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
READ CYCLE
Symbol
-65
-80
Unit
Parameter
Min
Max
Min
Max
Read Cycle Time
tRC
65
80
ns
Chip Select Access Time
tCE
65
80
ns
Address Access Time
tAA
65
80
ns
Output Enable Access Time
tOE
35
40
ns
Chip Select Low to Active Output
tLZ (1)
00
ns
Output Enable Low to Active Output
tOLZ (1)
00
ns
Chip Select High to Output in High Z
tHZ (1)
35
40
ns
Output Enable High to Output in High Z
tOHZ (1)
35
40
ns
Output Hold from Address Change
tOH
00
ns
NOTES:
1. tWC (min), tHZ, tOLZ (min), and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured, with CL = 5pF, from the point when CS, OE return High
(whichever occurs first) to the time when the outputs are no longer driven.
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