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參數(shù)資料
| 型號(hào)： | W986432DH-8 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
| 封裝： | 0.400 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 77K |
| 代理商： | W986432DH-8 |
W986432DH
- 8 -
AC CHARACTERISTICS
(VCC = 3.3V
± 0.3V, VSS = 0V, Ta = 0 to 70 °C) (Notes: 5, 6.)
PARAMETER
Symbol
-7
-8
UNIT
NOTE
MIN
MAX
MIN
MAX
MIN
MAX
Ref/Active to Ref/Active Command Period
tRC
65
68
ns
Active to precharge Command Period
tRAS
45
100000
48
100000
Active to Read/Write Command Delay Time tRCD
20
Read/Write(a) to Read/Write(b)Command
Period
tCCD
1
Cycle
Precharge to Active(b) Command Period
tRP
20
ns
Active(a) to Active(b) Command Period
tRRD
14
20
Write Recovery Time
CL* = 2
tWR
7.5
10
CL* = 3
7
8
CLK Cycle Time
CL* = 2
tCK
7.5
1000
10
1000
CL* = 3
7
1000
8
1000
CLK High Level
tCH
2
3
CLK Low Level
tCL
2
3
Access Time from CLK
CL* = 2
tAC
5.5
6
CL* = 3
5
6
Output Data Hold Time
tOH
3
Output Data High Impedance Time
tHZ
3
7
3
8
Output Data Low Impedance Time
tLZ
0
Power Down Mode Entry Time
tSB
0
7
0
8
Transition Time of CLK (Rise and Fall)
tT
0.5
10
0.5
10
Data-in-Set-up Time
tDS
0.5
2
Data-in Hold Time
tDH
1
Address Set-up Time
tAS
0.5
2
Address Hold Time
tAH
1
CKE Set-up Time
tCKS
0.5
2
CKE Hold Time
tCKH
1
Command Set-up Time
tCMS
0.5
2
Command Hold Time
tCMH
1
Refresh Time
tREF
64
ms
Mode Register Set Cycle Time
tRSC
14
16
ns
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