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參數(shù)資料
| 型號： | W986432DH-8 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
| 封裝： | 0.400 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 77K |
| 代理商： | W986432DH-8 |
PRELIMINARY W986432DH
512K
×× 4 BANKS ×× 32 BITS SDRAM
Publication Release Date: May 2000
- 2 -
Revision A0
PIN CONFIGURATION
86
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
37
38
39
40
41
42
43
28
29
30
31
32
33
34
35
36
50
49
48
47
46
45
44
58
57
56
55
54
53
52
51
85
V
ss
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
CC
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
CC
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
VCC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
VSSQ
DQ7
NC
VCC
DQM0
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
V
CC
NC
DQ16
V
SS
Q
DQ17
DQ18
V
CC
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
CC
Q
DQ23
V
CC
PIN DESCRIPTION
PIN NAME
FUNCTION
DESCRIPTION
A0
A10
Address
Multiplexed pins for row and column address.
Row address: A0
A10. Column address: A0A7.
A10 is sampled during a precharge command to determine if
all banks are to be precharged or bank selected by BS0, BS1.
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
DQ0
DQ31
Data Input/
Output
Multiplexed pins for data output and input.
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock RAS , CAS and WE define the operation to be
executed.
CAS
Column Address
Strobe
Referred to RAS
WE
Write Enable
Referred to RAS
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