- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄203637 > W986432DH-6 (WINBOND ELECTRONICS CORP) 2M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 PDF資料下載
參數(shù)資料
| 型號： | W986432DH-6 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| 封裝： | 0.400 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件頁數(shù)： | 46/48頁 |
| 文件大小： | 1648K |
| 代理商： | W986432DH-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當(dāng)前第46頁第47頁第48頁
W986432DH
Publication Release Date: July 30, 2002
- 7 -
Revision A5
7. FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and initialization
sequence need to be followed to guarantee the device being preconditioned to each user specific
needs.
During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V
on any of the input pins or VCC supplies. After power up, an initial pause of 200
S is required followed
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation. All
banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of
RAS ,
CAS ,
CS
and
WE
at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as TRAS (max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS
high and
CAS
low at the clock rising edge after minimum of tRCD delay.
WE
pin voltage
level defines whether the access cycle is a read operation ( WE
high), or a write operation ( WE
low). The address inputs determine the starting column address. Reading or writing to a different row
within an activated bank requires the bank be precharged and a new Bank Activate command be
issued. When more than one bank is activated, interleaved bank Read or Write operations are
possible. By using the programmed burst length and alternating the access and precharge operations
between multiple banks, seamless data access operation among many different pages can be
realized. Read or Write Commands can also be issued to the same bank or between active banks on
every clock cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W986432DH-8 | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
| W987Z6CBG80 | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| WA-1RVX051-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-1RX12-A4 | SNAP ACTING/LIMIT SWITCH |
| WB3M200VD1R800 | 200 CONTACT(S), MALE, STRAIGHT SINGLE PART CARD EDGE CONN, SURFACE MOUNT, PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W986432DH-6I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W986432DH-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W986432DH-7L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W9864G2DH6 | 制造商:WINBOND 功能描述:New |
| W9864G2GH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K X 4 BANKS X 32BITS SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。