
W83697UF
Publication Release Date: Dec. 2002
Revision 1.0
- I -
TABLE OF CONTENT
GENERAL DESCRIPTION..................................................................................................................... 1
PIN CONFIGURATION FOR 697UF ...................................................................................................... 5
1. PIN DESCRIPTION............................................................................................................................ 6
1.1 LPC I
NTERFACE
................................................................................................................................. 7
1.2 FDC I
NTERFACE
................................................................................................................................. 8
1.3 M
ULTI
-M
ODE
P
ARALLEL
P
ORT
............................................................................................................. 9
1.4 S
ERIAL
P
ORT
I
NTERFACE
.................................................................................................................. 14
1.5 I
NFRARED
P
ORT
............................................................................................................................... 15
1.6 F
LASH
ROM I
NTERFACE
................................................................................................................... 16
1.7 G
ENERAL
P
URPOSE
I/O P
ORT
........................................................................................................... 16
1.8 S
MART
C
ARD
I
NTERFACE
.................................................................................................................. 17
1.9 PWM & G
ENERAL
P
URPOSE
I/O P
ORT
8........................................................................................... 18
1.10 G
AME
P
ORT
& MIDI P
ORT
.............................................................................................................. 18
1.11 POWER PINS............................................................................................................................... 19
2. CONFIGURATION REGISTER ....................................................................................................... 20
2.1 P
LUG AND
P
LAY
C
ONFIGURATION
...................................................................................................... 20
2.2 C
OMPATIBLE
P
N
P............................................................................................................................. 20
2.2.1 Extended Function Registers .................................................................................................. 20
2.2.2 Extended Functions Enable Registers (EFERs) ..................................................................... 21
2.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs).... 21
2.3 C
ONFIGURATION
S
EQUENCE
............................................................................................................. 21
2.3.1 Enter the extended function mode........................................................................................... 21
2.3.2 Configurate the configuration registers ................................................................................... 21
2.3.3 Exit the extended function mode............................................................................................. 21
2.3.4 Software programming example.............................................................................................. 22
2.4 C
HIP
(G
LOBAL
) C
ONTROL
R
EGISTER
................................................................................................. 23
2.5 L
OGICAL
D
EVICE
0 (FDC)................................................................................................................. 31
2.6 L
OGICAL
D
EVICE
1 (P
ARALLEL
P
ORT
)................................................................................................ 36
2.7 L
OGICAL
D
EVICE
2 (UART A)........................................................................................................... 38
2.8 L
OGICAL
D
EVICE
3 (UART B)........................................................................................................... 39
2.9 L
OGICAL
D
EVICE
7 (G
AME
P
ORT AND
GPIO P
ORT
1)......................................................................... 42
2.10 L
OGICAL
D
EVICE
8 (MIDI P
ORT AND
GPIO P
ORT
5)........................................................................ 43
2.11 L
OGICAL
D
EVICE
9 (GPIO P
ORT
2
~ GPIO P
ORT
4 )....................................................................... 45
2.12 L
OGICAL
D
EVICE
A (ACPI).............................................................................................................. 47
2.13 L
OGICAL
D
EVICE
B (PWM)............................................................................................................. 52
2.14 L
OGICAL
D
EVICE
C (SMART CARD).............................................................................................. 53
2.15 L
OGICAL
D
EVICE
D (URC & GPIO P
ORT
6 )................................................................................... 53
2.16 L
OGICAL
D
EVICE
E (URD & GPIO P
ORT
7 ) ................................................................................... 54
2.17 L
OGICAL
D
EVICE
F (GPIO P
ORT
8)................................................................................................. 57
3. SPECIFICATIONS ........................................................................................................................... 58
3.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
.......................................................................................................... 58
3.2 DC CHARACTERISTICS............................................................................................................... 58