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參數(shù)資料
| 型號(hào)： | W78M64VP120SBM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA156 |
| 封裝： | 13 X 22 MM, PLASTIC, BGA-156 |
| 文件頁數(shù)： | 2/48頁 |
| 文件大?。?/td> | 1548K |
| 代理商： | W78M64VP120SBM |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
on the following read cycle. However, if after the initial two
read cycles, the system determines that the toggle bit is still
toggling, the system also should note whether the value of
DQ5 is high (see DQ5: Exceeded Timing Limits). If it is, the
system should then determine again whether the toggle bit
is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erases operation. If it is still toggling, the device did not
complete the operation successfully, and the system must
write the reset command to return to reading array data. The
remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5 has not gone high.
The system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when
it returns to determine the status of the operation. Refer to
FIG: 7 for more details.
NOTE
When verifying the status of a write operation (embedded
program/erase) of a memory sector, DQ6 and DQ2 toggle
between high and low states in a series of consecutive and
contiguous status read cycles. In order for this toggling
behavior to be properly observed, the consecutive status bit
reads must not be interleaved with read accesses to other
memory sectors. If it is not possible to temporarily prevent
reads to other memory sectors, then it is recommended
to use the DQ7 status bit as the alternative method of
determining the active or inactive status of the write
operation.
DQ5: Exceeded Timing
Limits
DQ5 indicates whether the program or erase time has
exceeded a specied internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed. The device
does not output a 1 on DQ5 if the system tries to program a
1 to a location that was previously programmed to 0. Only
an erase operation can change a 0 back to a 1. Under this
condition, the device ignores the bit that was incorrectly
instructed to be programmed from a 0 to a 1, while any
other bits that were correctly requested to be changed from
1 to 0 are programmed. Attempting to program a 0 to a 1
is masked during the programming operation. Under valid
DQ5 conditions, the system must write the reset command
to return to the read mode (or to the erase-suspend-read
mode if a sector was previously in the erase-suspend-
program mode).
DQ3: Sector Erase Timeout
State Indicator
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not erasure
has begun. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected
for erasure, the entire time-out also applies after each
additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” If the time
between additional sector erase commands from the system
can be assumed to be less than tSEA, then the system need
not monitor DQ3. See Sector Erase for more details.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the
command sequence, and then read DQ3. If DQ3 is “1,”
the Embedded Erase algorithm has begun; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the device
accepts additional sector erase commands. To ensure
the command has been accepted, the system software
should check the status of DQ3 prior to and following each
sub-sequent sector erase command. If DQ3 is high on the
second status check, the last command might not have
been accepted. Table 18 shows the status of DQ3 relative
to the other status bits.
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was
aborted. Under these conditions DQ1 produces a “1”.
The system must issue the “Write to Buffer Abort Reset”
command sequence to return the device to reading array
data. See Write Buffer Programming for more details.
Writing Commands/
Command Sequences
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