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參數(shù)資料
| 型號： | W78M64V100SBC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM MODULE, 100 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 34/54頁 |
| 文件大?。?/td> | 1348K |
| 代理商： | W78M64V100SBC |
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4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64V-XSBX
July 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is a latch used to store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs
to the internal state machine. The state machine outputs
dictate the function of the device. Table 1 lists the device
bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe
each of these operations in further detail.
TABLE 1. DEVICE BUS OPERATION3
Operation
CS#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A22-A0)
DQ15-DQ0
Read
LL
H
X
AIN
DOUT
Write
LH
L
H
X
AIN
DIN
Standby
VIO±
0.3 V
XX
VIO ±
0.3 V
X (Note 2)
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
Temporary Sector Unprotect (High
Voltage
XX
X
VID
XAIN
DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 8.5-9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In,
DOUT = Data Out
Notes:
1.
The sector protect and sector unprotect functions may also be Implemented via programming equipment. See the High Voltage Sector Protection section.
2.
WP#/ACC must be high when writing to sectors 0, 1, 268, or 269.
3.
For each chip
REQUIREMENTS FOR READING
ARRAY DATA
To read array data from the outputs, the system must drive
the OE# and appropriate CS# pins to VIL. CS# is the power
control. OE# is the output control and gates array data to
the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device
address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until
the command register contents are altered.
Refer to theAC Characteristics table for timing specications
and to Figure 11 for the timing diagram. ICC1 in the
DC Characteristics table represents the active current
specication for reading array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable
addresses to valid output data. The chip enable access
time (tCS) is the delay from the stable addresses and stable
CS# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE#
to valid data at the output inputs (assuming the addresses
have been stable for at least tACC–tOE time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. Address bits A22–A3 select an 8
word page, and address bits A2–A0 select a specic word
within that page. This is an asynchronous operation with the
microprocessor supplying the specic word location.
The random or initial page access is tACC or tCS and
subsequent page read accesses (as long as the locations
specied by the microprocessor falls within that page) is
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