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參數(shù)資料
| 型號： | W78M64V100SBC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM MODULE, 100 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 1348K |
| 代理商： | W78M64V100SBC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64V-XSBX
July 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and veries the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
Table 13 shows the address and data requirements for the
chip erase command sequence.
When the Embedded Erase algorithm is complete, that
bank returns to the read mode and addresses are no longer
latched. The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to
the Write Operation Status section for information on these
status bits.
Any commands written during the chip erase operation
are ignored. Note that SecSi Sector, autoselect, and CFI
functions are unavailable when a [program/erase] operation
is in progress.
However, note that a hardware reset
immediately terminates the erase operation. If that occurs,
the chip erase command sequence should be reinitiated
once that bank has returned to reading array data, to ensure
data integrity.
Figure 7 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the
AC Characteristics section for parameters, and Figure 17
section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock cycles
are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
13 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
programs and veries the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-
out of 50 μs occurs. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50 μs, otherwise erasure may begin. Any sector
erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to ensure
all commands are accepted. The interrupts can be re-
enabled after the last Sector Erase command is written. Any
command other than Sector Erase or Erase Suspend
during the time-out period resets that bank to the read
mode.
The system must rewrite the command sequence
and any additional addresses and commands. Note that
SecSi Sector, autoselect, and CFI functions are unavailable
when a [program/erase] operation is in progress.
The system can monitor DQ3 to determine if the sector
erase timer has timed out (See the section on DQ3: Sector
Erase Timer). The time-out begins from the rising edge of
the nal WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank
returns to reading array data and addresses are no longer
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
FIGURE 6. PROGRAM OPERATION
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