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參數(shù)資料
| 型號： | W78M64110SBM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM, 110 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 47/50頁 |
| 文件大小： | 1679K |
| 代理商： | W78M64110SBM |
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6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
November 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specications without notice.
The Write Buffer Programming Sequence is ABORTED
under any of the following conditions:
Load a value that is greater than the page buffer size
during the “Number of Locations to Program” step.
Write to an address in a sector different than the one
specied during the Write-Buffer-Load command.
Write an Address/Data pair to a different write-
buffer-page than the one selected by the “Starting
Address” during the “write buffer data loading” stage
of the operation.
Writing anything other than the Program to Buffer
Flash Command after the specied number of “data
load” cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7
= DATA# (for the “l(fā)ast address location loaded”),
DQ6 = TOGGLE, DQ5 = 0. This indicates that
the Write Buffer Programming Operation was
ABORTED. A “Write-to- Buffer-Abort reset” command
sequence is required when using the write buffer
Programming features in Unlock Bypass mode. Note
that the Secured Silicon sector, autoselect, and CFI
functions are unavailable when a program operation
is in progress.
Write buffer programming is allowed in any sequence of
memory (or address) locations. These ash devices are
capable of handling multiple write buffer programming
operations on the same write buffer address range without
intervening erases.
Use of the write buffer is strongly recommended for
programming when multiple words are to be programmed.
SECTOR ERASE
The sector erase function erases one or more sectors in the
memory array. (See Table 38 and FIG: 6.) The device does
not require the system to preprogram a sector prior to erase.
The Embedded Erase algorithm automatically programs
and veries the entire memory to an all zero data pattern
prior to electrical erase. After a successful sector erase,
all locations within the erased sector contain FFFFh. The
system is not required to provide any controls or timings
during these operations.
After the command sequence is written, a sector erase time-
out of no less than tSEA occurs. During the timeout period,
additional sector addresses may be written. Loading the
sector erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50
μs. Any sector erase address and command following the
exceeded time-out (50μs) may or may not be accepted. Any
command other than Sector Erase or Erase Suspend during
the time-out period resets that sector to the read mode. The
system can monitor DQ3 to determine if the sector erase
timer has timed out. The time-out begins from the rising edge
of the nal WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the
sector returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing
sector. Refer to Section write operation status section for
information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the sector
erase command sequence should be reinitiated once that
sector has returned to reading array data, to ensure the
sector is properly erased.
The Unlock Bypass feature allows the host system to send
program commands to the Flash device without rst writing
unlock cycles within the command sequence. See Unlock
Bypass Section for details on the Unlock Bypass function.
FIG: 6 illustrates the algorithm for the erase operation.
Refer to Erase and Programming Performance Section for
parameters and timing diagrams.
CHIP ERASE COMMAND SEQUENCE
Chip erase is a six-bus cycle operation as indicated by
Table 39. These commands invoke the Embedded Erase
algorithm, which does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically
preprograms and veries the entire memory to an all zero
data pattern prior to electrical erase. After a successful chip
erase, all locations of the chip contain FFFFh. The system
is not required to provide any controls or timings during
these operations. The Command Denitions shows the
address and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, that
sector returns to the read mode and addresses are no
longer latched. The system can determine the status of the
erase operation by using DQ7 or DQ6/DQ2. Refer to “Write
Operation Status” for information on these status bits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W78M64110SBI | 8M X 64 FLASH 3.3V PROM, 110 ns, PBGA159 |
| W78M64120SBI | 8M X 64 FLASH 3.3V PROM, 120 ns, PBGA159 |
| W78M64110SBC | 8M X 64 FLASH 3.3V PROM, 110 ns, PBGA159 |
| W78M64V100SBC | 8M X 64 FLASH 3.3V PROM MODULE, 100 ns, PBGA159 |
| W78M64VP120SBM | SPECIALTY MEMORY CIRCUIT, PBGA156 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W78M64VP110SBM | 制造商:Microsemi Corporation 功能描述:8MX64 FLASH 3.3V PAGE MODE - Bulk |
| W78M64V-XSBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash MCP |
| W78NCSX-23 | 功能描述:低信號繼電器 - PCB 4PDT 3A 24VDC IND RoHS:否 制造商:NEC 觸點形式:2 Form C (DPDT-BM) 觸點電流額定值: 線圈電壓:5 V 最大開關(guān)電流:1 A 線圈電流:1 A 線圈類型:Non-Latching 功耗:140 mW 端接類型:SMT 絕緣: 介入損耗: |
| W78PCX-1 | 制造商:Magnecraft 功能描述: |
| W78PCX-2 | 制造商:Magnecraft 功能描述: |
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