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參數(shù)資料
| 型號(hào)： | W78M64110SBM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM, 110 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 2/50頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | W78M64110SBM |
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10
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
November 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specications without notice.
NOTE
When verifying the status of a write operation (embedded
program/erase) of a memory sector, DQ6 and DQ2 toggle
between high and low states in a series of consecutive and
contiguous status read cycles. In order for this toggling
behavior to be properly observed, the consecutive status bit
reads must not be interleaved with read accesses to other
memory sectors. If it is not possible to temporarily prevent
reads to other memory sectors, then it is recommended
to use the DQ7 status bit as the alternative method of
determining the active or inactive status of the write
operation.
DQ5: EXCEEDED TIMING LIMITS
DQ5 indicates whether the program or erase time has
exceeded a specied internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed. The device
does not output a 1 on DQ5 if the system tries to program a
1 to a location that was previously programmed to 0. Only
an erase operation can change a 0 back to a 1. Under this
condition, the device ignores the bit that was incorrectly
instructed to be programmed from a 0 to a 1, while any
other bits that were correctly requested to be changed from
1 to 0 are programmed. Attempting to program a 0 to a 1
is masked during the programming operation. Under valid
DQ5 conditions, the system must write the reset command
to return to the read mode (or to the erase-suspend-read
mode if a sector was previously in the erase-suspend-
program mode).
DQ3: SECTOR ERASE TIMEOUT STATE
INDICATOR
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not erasure
has begun. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected
for erasure, the entire time-out also applies after each
additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” If the time
between additional sector erase commands from the system
can be assumed to be less than tSEA, then the system need
not monitor DQ3. See Sector Erase for more details.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the
command sequence, and then read DQ3. If DQ3 is “1,”
the Embedded Erase algorithm has begun; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the device
accepts additional sector erase commands. To ensure
the command has been accepted, the system software
should check the status of DQ3 prior to and following each
sub-sequent sector erase command. If DQ3 is high on the
second status check, the last command might not have
been accepted. Table 18 shows the status of DQ3 relative
to the other status bits.
DQ1: WRITE TO BUFFER ABORT
DQ1 indicates whether a Write to Buffer operation was
aborted. Under these conditions DQ1 produces a “1”.
The system must issue the “Write to Buffer Abort Reset”
command sequence to return the device to reading array
data. See Write Buffer Programming for more details.
WRITING COMMANDS/COMMAND
SEQUENCES
During a write operation, the system must drive CE# and
WE# to VIL and OE# to VIH when providing an address,
command, and data. Addresses are latched on the last
falling edge of WE# or CE#, while data is latched on the 1st
rising edge of WE# or CE#. An erase operation can erase
one sector, multiple sectors, or the entire device. Table 1
indicate the address space that each sector occupies. The
device address space is divided into uniform 64KW/128KB
sectors. A sector address is the set of address bits required
to uniquely select a sector. ICC2 in “DC Characteristics”
represents the active current specication for the write
mode. “AC Characteristics” contains timing specication
tables and timing diagrams for write operations.
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress or
complete. The RY/BY# status is valid after the rising edge of
the nal WE# pulse in the command sequence. Since RY/
BY# is an open-drain output, several RY/BY# pins can be
tied together in parallel with a pull-up resistor to VCC. This
feature allows the host system to detect when data is ready
to be read by simply monitoring the RY/BY# pin, which is a
dedicated output and controlled by CE# (not OE#).
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| W78M64110SBI | 8M X 64 FLASH 3.3V PROM, 110 ns, PBGA159 |
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| W78M64110SBC | 8M X 64 FLASH 3.3V PROM, 110 ns, PBGA159 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W78M64VP110SBM | 制造商:Microsemi Corporation 功能描述:8MX64 FLASH 3.3V PAGE MODE - Bulk |
| W78M64V-XSBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash MCP |
| W78NCSX-23 | 功能描述:低信號(hào)繼電器 - PCB 4PDT 3A 24VDC IND RoHS:否 制造商:NEC 觸點(diǎn)形式:2 Form C (DPDT-BM) 觸點(diǎn)電流額定值: 線圈電壓:5 V 最大開關(guān)電流:1 A 線圈電流:1 A 線圈類型:Non-Latching 功耗:140 mW 端接類型:SMT 絕緣: 介入損耗: |
| W78PCX-1 | 制造商:Magnecraft 功能描述: |
| W78PCX-2 | 制造商:Magnecraft 功能描述: |
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