參數(shù)資料
型號(hào)： W78E058B40PL
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝： ROHS COMPLIANT, PLASTIC, LCC-44
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 406K
代理商： W78E058B40PL
W78E58B/W78E058B
Publication Release Date: December 4, 2006
- 7 -
Revision A8
5.3 Clock
The W78E058B is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E058B relatively insensitive to duty
cycle variations in the clock.
5.4 Crystal Oscillator
The W78E058B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.
5.5 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
5.6 Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to
the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a
hardware reset or external interrupts
INT0
to
INT1
when enabled and set to level triggered.
5.7 Reduce EMI Emission
The W78E058B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.
5.8 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E058B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
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