參數(shù)資料
型號(hào)： W78E058B40PL
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝： ROHS COMPLIANT, PLASTIC, LCC-44
文件頁(yè)數(shù)： 13/36頁(yè)
文件大?。?/td> 406K
代理商： W78E058B40PL
W78E58B/W78E058B
Publication Release Date: December 4, 2006
- 13 -
Revision A8
ADDRESS BUS
Bit Length
Selectable
comparator
REGISTER
P4xAL
P4xAH
EQUAL
P4.x
MUX 4->1
WR_CS
P4 REGISTER
P4.x
READ
WRITE
DATA I/O
RD_CS
RD/WR_CS
P4xCMP0
P4xCMP1
P4xFUN0
P4xFUN1
P4xCSINV
P4.x INPUT DATA BUS
REGISTER
PIN
5.12 In-System Programming (ISP) Mode
The W78E058B equips one 32K byte of main ROM bank for application program (called APROM) and
one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the
microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the
W78E058B allows user to activate the In-System Programming (ISP) mode by setting the CHPCON
register.
The CHPCON is read-only by default,
software
must write two specific values 87H,
then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing
CHPENR register with the values except 87H and 59H will close CHPCON register write
attribute.
The W78E058B achieves all in-system programming operations including enter/exit ISP
Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the
device will enter in-system programming mode after a wake-up from idle mode. Because device
needs proper time to complete the ISP operations before awaken from idle mode, software may use
timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for
revising contents of APROM, software located at APROM setting the CHPCON register then enter idle
mode, after awaken from idle mode the device executes the corresponding interrupt service routine in
LDROM. Because the device will clear the program counter while switching from APROM to LDROM,
the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The
device offers a software reset for switching back to APROM while the content of APROM has been
updated completely.
Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset
to reset the CPU
. The software reset serves as a external reset. This in-system programming feature
makes the job easy and efficient in which the application needs to update firmware frequently. In some
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