參數(shù)資料
型號: W78CE354
廠商: WINBOND ELECTRONICS CORP
英文描述: MONITOR MICROCONTROLLER
中文描述: 顯示器單片機
文件頁數(shù): 38/44頁
文件大?。?/td> 426K
代理商: W78CE354
W78C354
- 38 -
N. Power Supervisor, Watchdog Timer, and Reset Circuitry
Reset signals can come from three sources: an external reset input (active low), power-low detection,
or the watchdog timer. Figure 20 is a block diagram of the reset circuitry. The power-low detection
circuit generates a reset signal if V
CC
falls below 3.8V, and the reset signal will keep twenty-four
machine cycle after V
CC
rises to 4.3V. Thus we can make sure the chip can be reseted perfectly
when the monitor is first powered on, and avoid the w78c354's overwriting the E
2
PROM mistakenly
when the monitor is powered down. The power-low detection circuit can be enabled or disabled by
code option 1.
The purpose of the watchdog timer is to reset the W78C354 if it enters an abnormal processor state
(caused by electrical noise or RFI, for example). The clock source of the watchdog timer comes from
the internal system clock. The timer can be enabled or disabled by the code option 2. When enabled,
the watchdog circuitry will generate a system reset if the user's program fails to reload the watchdog
timer within a specified length of time after executing the "MOV WDTCLR, # Value" instruction. This
length of time is known as the "watchdog interval" (T
WDT
). Four selections are available for the
watchdog interval (type A, B, C, and D); the selections, which are programmed by code option 3, are
indicated by the formulas in table below.
There are three code options in the reset circuitry:
Code option 1: Enable/disable the power-low detector.
Code option 2: Enable/disable the watchdog timer.
Code option 3: Select one watchdog interval (type A, B, C, D as listed in the table below.)
Watchdog
Timer
Power-low
Detector
Enable/Disable
External reset
System Reset
Code option 2
Code option 1
Enable/Disable
Code option 3
Watchdog interval
Figure 20. Reset circuitry
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