
W78C354
Publication Release Date: October 1996
- 13 -
Revision A1
3. CONTREG2: Control Register2, continued
BIT
NAME
4
EINTES
FUNCTION
External INT Edge Select.
0: High-level/rising-edge triggered.
1: Low-level/falling-edge triggered.
Enable/Disable SDAC0 morie cancel function.
0: Disable, 1: Enable.
Enable/Disable SDAC1 morie cancel function.
0: Disable, 1: Enable.
Disable H-Clamp pulse at the Vsync pulse period. In initial state, it
enables the H-Clamp output.
0: Enable, 1: Disable.
5
ENM0
6
ENM1
7
VDISHC
4. CONTREG4: Control Register4, Bit-addressable
BIT
0
NAME
P24SF
FUNCTION
Enable/Disable Port 2.4 Special Function.
P24SF = 0: General I/0 pin.
P24SF = 1 and P2.4 = 0: SDAC10 output.
Enable/Disable Port 2.5 Special Function.
P25SF = 0: General I/0 pin.
P25SF = 1 and P2.5 = 0: SDAC11 output.
Enable/Disable Port 2.6 Special Function.
P26SF = 0: General I/0 pin.
P26SF = 1 and P2.6 = 0: SDAC12 output.
Enable/Disable Port 2.7 Special Function.
P27SF = 0: General I/0 pin.
P27SF = 1 and P2.7 = 0: SDAC13 output.
Enable/Disable Port 1.4 Special Function.
P14SF = 0: General I/0 pin.
P14SF = 1 and P1.4 = 0: H-Clamp output.
Enable/Disable Port 1.5 Special Function.
P15SF = 0: General I/0 pin.
P15SF = 1 and P1.5 = 0: SOA output.
Enable/Disable Port 2.3 Special Function.
P23SF = 0: General I/0 pin.
P23SF = 1 and P2.3 = 0: STP output.
Invert Self-Test Pattern.
1
P25SF
2
P26SF
3
P27SF
4
P14SF
5
P15SF
6
P23SF
7
INVSTP
Note: To let the Px.y output special function, set PxySF and clear Px.y.